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| ST72141K 8-BIT MCU WITH ELECTRIC-MOTOR CONTROL, ADC, 16-BIT TIMERS, SPI INTERFACE s s s s s s s Memories - 8K Program memory (ROM/OTP/EPROM) - 256 Bytes RAM Clock, Reset and Supply Management - Enhanced reset system - Low voltage supply supervisor - 3 Power saving modes 14 I/O Ports - 14 multifunctional bidirectional I/O lines with: External interrupt capability (2 vectors), 13 alternate function lines, 3 high sink outputs Motor Control peripheral - 6 PWM output channels - Emergency pin to force outputs to HiZ state - 3 analog inputs for rotor position detection with no need for additional sensors - Comparator for current limitation 3 Timers - Two 16-bit timers with: 2 input captures, 2 output compares, external clock input, PWM and Pulse generator modes - Watchdog timer for system integrity Communications Interface - SPI synchronous serial interface Analog Peripheral - 8-bit ADC with 8 input pins SDIP32 SO34S s s Instruction Set - 8-bit data manipulation - 63 basic instructions - 17 main addressing modes - 8 x 8 unsigned multiply instruction - True bit manipulation Development Tools - Full hardware/software development package ST72141K2 Device Summary Features Program memory - bytes RAM (stack) - bytes Peripherals Operating Supply CPU Frequency Operating Temperature Packages 8K 256 (64) Motor control, Watchdog, Two 16-bit timers, SPI, ADC 4V to 5.5V 4 or 8 MHz (with 8 or 16 MHz oscillator) -40C to +85C / -40C to +125C SO34 / SDIP32 Rev. 1.8 October 2001 1/132 1 Table of Contents 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 EPROM PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 RESET MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 3.3 LOW CONSUMPTION OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 31 31 34 6.3.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 I/O PORT INTERRUPT SENSITIVITY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3 CLOCK PRESCALER SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 MOTOR CONTROLLER (MTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1.1 8.1.2 8.1.3 8.1.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 . ... Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 44 2/132 2 Table of Contents 8.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 66 67 75 75 75 76 76 76 76 78 78 78 78 90 90 90 91 96 8.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.5 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 109 110 110 110 111 112 112 113 113 113 113 113 114 114 115 10 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 10.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3/132 3 Table of Contents 10.4 GENERAL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10.5 I/O PORT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10.6 SUPPLY, RESET AND CLOCK CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.6.1Supply Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.2RESET Sequence Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6.3Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.7 MEMORY AND PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 121 121 122 11 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 11.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 11.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 12 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 132 4/132 1 ST72141K 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST72141K devices are members of the ST7 microcontroller family designed specifically for motor control applications and including A/D conversion and SPI interface capabilities. They include an on-chip Moter Controller peripheral for control of electric brushless moters with or without sensors. An example application, for 6-step control of a Permanent Magnet DC motor, is shown in Figure 1. The ST72141K devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. Under software control, they can be placed in WAIT, SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. Figure 1. Example of a 6-step-controlled Motor ST7 MO C 5-0 6 300V 0 2 B I1 I6 4 M IB C MTC M IA C M IC C A I4 I3 I5 3 5 I2 C 1 Net 1 2 3 4 Step 5 6 1 2 3 0 1 2 3 4 5 A B C 300V 150V 0 300V 150V 0 300V 150V 0 Figure 2. Device Block Diagram Internal CLOCK OSC OSC2 VDD VSS RESET POWER SUPPLY LVD DIV 8-BIT ADC TIMER B TIMER A CONTROL ADDRESS AND DATA BUS OSC1 PORT A PA7:0 (8-BIT) OC1A MCO5:0 MCIA:C MOTOR CTRL MCES MCCFI PORT B SPI PB5:0 (6-BIT) 8-BIT CORE ALU 8K-EPROM 256b-RAM WATCHDOG 5/132 4 ST72141K 1.2 PIN DESCRIPTION Figure 3. 34-Pin SO Package Pinout MCO5 MCO4 MCO3 MCO2 MCO1 MCO0 MCES MISO/PB5 NC MOSI/PB4 SCK/PB3 SS/ (HS) PB2 EXTCLK_B/ (HS) PB1 EXTCLK_A/ (HS) PB0 OSC1 OSC2 RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 EI0 EI1 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 MCIA MCIB MCIC MCCFI VDD VSS VPP OCMP1_A NC PA7/AIN7/OCMP2_A PA6/AIN6/ICAP1_A PA5/AIN5/ICAP2_A PA4/AIN4/OCMP1_B PA3/AIN3/OCMP2_B PA2/AIN2/ICAP1_B PA1/AIN1/ICAP2_B PA0/AIN0 Figure 4. 32-Pin SDIP Package Pinout MCO5 MCO4 MCO3 MCO2 MCO1 MCO0 MCES MISO/PB5 MOSI/PB4 SCK/PB3 SS/ (HS) PB2 EXTCLK_B/ (HS) PB1 EXTCLK_A/ (HS) PB0 OSC1 OSC2 RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EI0 32 31 30 29 28 27 26 25 24 23 22 EI1 21 20 19 18 17 MCIA MCIB MCIC MCCFI VDD VSS VPP OCMP1_A PA7/AIN7/OCMP2_A PA6/AIN6/ICAP1_A PA5/AIN5/ICAP2_A PA4/AIN4/OCMP1_B PA3/AIN3/OCMP2_B PA2/AIN2/ICAP1_B PA1/AIN1/ICAP2_B PA0/AIN0 6/132 5 ST72141K PIN DESCRIPTION (Cont'd) Legend / Abbreviations: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD, CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = high sink (on N-buffer only), R = 70/100 ratio of logical levels. Analog level if used as PWM filtered with an external capacitor Port configuration capabilities: - Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog - Output: OD = open drain, T = true open drain, PP = push-pull Note: the Reset configuration of each pin is shown in bold. Table 1. Device Pin Description Pin n Type SDIP32 SO34 Pin Name Level Output Input Port / Control Input float wpu ana int Output OD PP Main Function (after reset) Alternate Function 1 2 3 4 5 6 7 8 1 MCO5 2 MCO4 3 MCO3 4 MCO2 5 MCO1 6 MCO0 7 MCES 8 PB5/MISO 9 NC O O O O O O I I/O CT C C C C C C X X EI1 X X X X X X X Motor Control Output Channel 5 Motor Control Output Channel 4 Motor Control Output Channel 3 Motor Control Output Channel 2 Motor Control Output Channel 1 Motor Control Output Channel 0 Motor Control Emergency Stop Input CT X Port B5 SPI Master In / Slave Out Data Not Connected I/O I/O CT CT X X X X X EI1 EI1 EI1 EI1 EI1 X X T T T X X Port B4 Port B3 Port B2 Port B1 Port B0 SPI Master Out / Slave In Data SPI Serial Clock SPI Slave Select (active low) Timer B Input Clock Timer A Input Clock 9 10 PB4/MOSI 10 11 PB3/SCK 11 12 PB2/SS 12 13 PB1/EXTCLK_B 13 14 PB0/EXTCLK_A 14 15 OSC1 15 16 OSC2 16 17 RESET 17 18 PA0/AIN0 18 19 PA1/ICAP2_B/AIN1 19 20 PA2/ICAP1_B/AIN2 I/O CT HS I/O CT HS I/O CT HS These pins connect a crystal or ceramic resonator, or an external RC, or an external source to the on-chip oscillator I/O I/O I/O I/O C CT CT CT X X X X EI0 EI0 EI0 X X X X X X X X X X Top priority non maskable interrupt (active low) Port A0 Port A1 Port A2 ADC Analog Input 0 Timer B Input Capture 2 or ADC Analog Input 1 Timer B Input Capture 1 or ADC Analog Input 2 7/132 6 ST72141K Pin n Type SDIP32 SO34 Pin Name Level Output Input Port / Control Input float wpu ana int Output OD PP Main Function (after reset) Alternate Function 20 21 PA3/OCMP2_B/AIN3 21 22 PA4/OCMP1_B/AIN4 22 23 PA5/ICAP2_A/AIN5 23 24 PA6/ICAP1_A/AIN6 24 25 PA7/OCMP2_A/AIN7 26 NC 25 27 OCMP1_A 26 28 VPP 27 29 VSS 28 30 VDD 29 31 MCCFI 30 32 MCIC 31 33 MCIB 32 34 MCIA I/O I/O I/O I/O I/O CT CT CT CT CT X X X X X EI0 EI0 EI0 EI0 EI0 X X X X X X X X X X X X X X X Port A3 Port A4 Port A5 Port A6 Port A7 Timer B Output Compare 2 or ADC Analog Input 3 Timer B Output Compare 1 or ADC Analog Input 4 Timer A Input Capture 2 or ADC Analog Input 5 Timer A Input Capture 1 or ADC Analog Input 6 Timer A Output Compare 2 or ADC Analog Input 7 Not Connected O I S S I I I I A A A A R Timer A Output Compare 1 Must be tied low during normal operating mode,EPROM Programming voltage pin. Ground Main power supply Motor Control Current Feedback Input Motor Control Input C Motor Control Input B Motor Control Input A 8/132 ST72141K 1.3 EXTERNAL CONNECTIONS The following figure shows the recommended external connections for the device. The VPP pin is only used for programming OTP and EPROM devices and must be tied to ground in user mode. The 10 nF and 0.1 F decoupling capacitors on the power supply lines are a suggested EMC performance/cost tradeoff. Figure 5. Recommended External Connections The external reset network is intended to protect the device against parasitic resets, especially in noisy environments. Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines. An alternative solution is to program the unused ports as inputs with pull-up. VPP VDD 10F + VDD 0.1F VSS Optional if Low Voltage Detector (LVD) is used VDD VDD 4.7K 0.1F EXTERNAL RESET CIRCUIT 0.1F RESET VSS See Clocks Section OSC1 OSC2 Or configure unused I/O ports by software as input with pull-up VDD 10K Unused I/O 9/132 ST72141K 1.4 REGISTER & MEMORY MAP As shown in Figure 6, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, 256 bytes of RAM and 8Kbytes of user program memory. The RAM Figure 6. Memory Map 0080h 0000h 007Fh 0080h space includes up to 64 bytes for the stack from 0140h to 017Fh. The highest address bytes contain the user reset and interrupt vectors. HW Registers (see Table 3) Short Addressing RAM "Zero page" (128 Bytes) 00FFh 0100h 256 Bytes RAM 017Fh 0180h Reserved DFFFh E000h 16-bit Addressing RAM (64 Bytes) 013Fh 0140h Program Memory (8K Bytes) FFDFh FFE0h FFFFh Interrupt & Reset Vectors (see Table 2) 017Fh Stack or 16-bit Addressing RAM (64 Bytes) Table 2. Interrupt Vector Map Vector Address FFE0-FFE1h FFE2-FFE3h FFE4-FFE5h FFE6-FFE7h FFE8-FFE9h FFEA-FFEBh FFEC-FFEDh FFEE-FFEFh FFF0-FFF1h FFF2-FFF3h FFF4-FFF5h FFF6-FFF7h FFF8-FFF9h FFFA-FFFBh FFFC-FFFDh FFFE-FFFFh Description Not used Not used Not used Not used Not used TIMER B interrupt vector TIMER A interrupt vector SPI interrupt vector Motor control interrupt vector (events: E, O) Motor control interrupt vector (events: C, D) Motor control interrupt vector (events: R, Z) External interrupt vector EI1: port B7..0 External interrupt vector EI0: port A7..0 Not used TRAP (software) interrupt vector RESET vector Remarks Internal Interrupt External Interrupt External Interrupt CPU Interrupt 10/132 ST72141K Table 3. Hardware Register Map Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h to 001F 0020h 0021h 0022h 0023h 0024h 0025h 0026h to 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer SPI MISCR SPIDR SPICR SPISR WDGCR WDGSR Port B PBDR PBDDR PBOR Block Register Label PADR PADDR PAOR Register Name Port A Data Register Port A Data Direction Register Port A Option Register Reserved Area (1 Byte) Port B Data Register Port B Data Direction Register Port B Option Register Reserved Area (24 Byte) Miscellaneous Register SPI Data I/O Register SPI Control Register SPI Status Register Watchdog Control Register Watchdog Status Register Reserved Area (11 Bytes) A Control Register 2 A Control Register 1 A Status Register A Input Capture 1 High Register A Input Capture 1 Low Register A Output Compare 1 High Register A Output Compare 1 Low Register A Counter High Register A Counter Low Register A Alternate Counter High Register A Alternate Counter Low Register A Input Capture 2 High Register A Input Capture 2 Low Register A Output Compare 2 High Register A Output Compare 2 Low Register Reserved Area (1 Byte) 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 00h xxh 0xh 00h 7Fh x0h R/W R/W R/W Read Only R/W Read Only 00h 00h 00h R/W R/W R/W. Reset Status 00h 00h 00h Remarks R/W R/W R/W Port A WATCHDOG TIMER A 11/132 ST72141K Address 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h to 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh to 006Fh 0070h 0071h 0072h to 007Fh Block Register Label TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Register Name B Control Register 2 B Control Register 1 B Status Register B Input Capture 1 High Register B Input Capture 1 Low Register B Output Compare 1 High Register B Output Compare 1 Low Register B Counter High Register B Counter Low Register B Alternate Counter High Register B Alternate Counter Low Register B Input Capture 2 High Register B Input Capture 2 Low Register B Output Compare 2 High Register B Output Compare 2 Low Register Reserved Area (16 Bytes) Reset Status 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h Remarks R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W TIMER B MOTOR CONTROL MTIM MZPRV MZREG MCOMP MDREG MWGHT MPRSR MIMR MISR MCRA MCRB MPHST MPAR MPOL Timer Counter Register Zn-1 Capture Register Zn Capture Register Cn+1Compare Register D capture/Compare Register Weight Register Prescaler and Ratio Register Interrupt Mask Register Interrupt Status Register Control Register A Control Register B Phase State Register Output Parity Register Output Polarity Register Reserved Area (2 bytes) 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ADC ADCDR ADCCSR Data Register Control/Status Register Reserved Area (14 Bytes) 00h 00h Read Only R/W 12/132 ST72141K 1.5 EPROM PROGRAM MEMORY The program memory of the OTP and EPROM devices can be programmed with EPROM programming tools available from STMicroelectronics. EPROM Erasure EPROM devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current. It is recommended that the EPROM devices be kept out of direct sunlight, since the UV content of sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent lighting may also cause erasure. An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting conditions. Covering the window also reduces IDD in power-saving modes due to photo-diode leakage currents. 13/132 ST72141K 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 2.2 MAIN FEATURES s s s s s s s s 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes Maskable hardware interrupts Non-maskable software interrupt 2.3 CPU REGISTERS The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions. Figure 7. CPU Registers 7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 0 0 0 Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). ACCUMULATOR X INDEX REGISTER Y INDEX REGISTER PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 111HI 0 NZC CONDITION CODE REGISTER RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 14/132 ST72141K CPU REGISTERS (Cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx 7 1 1 1 H I N Z 0 C because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. 15/132 ST72141K CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh 15 0 7 0 SP6 SP5 SP4 SP3 SP2 SP1 0 0 0 0 0 0 8 1 0 SP0 The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 128 bytes deep, the 9th most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address. Figure 8. Stack Manipulation Example CALL Subroutine @ 0100h Interrupt Event PUSH Y The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8. - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. POP Y IRET RET or RSP SP SP CC A X PCH SP PCH @ 017Fh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP Stack Higher Address = 017Fh Stack Lower Address = 0100h 16/132 ST72141K 3 SUPPLY, RESET AND CLOCK MANAGEMENT The ST72141K includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 9. Main Features s Main supply low voltage detection (LVD) s RESET Manager s Low consumption resonator oscillator s Main clock controller (MCC) Figure 9. Clock, RESET, Option and Supply Management Overview fMOTOR_CONTROL fSPI MAIN CLOCK CONTROLLER (MCC) fCPU OSC2 OSCILLATOR OSC1 fOSC RESET RESET FROM WATCHDOG PERIPHERAL VDD VSS LOW VOLTAGE DETECTOR (LVD) 17/132 ST72141K 3.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VLVDf reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The V LVDf reference value for a voltage drop is lower than the V LVDr reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: - VLVDr when VDD is rising - VLVDf when VDD is falling The LVD function is illustrated in Figure 10. Figure 10. Low Voltage Detector vs Reset VDD Provided the minimum VDD value (guaranteed for the oscillator frequency) is below VLVDf, the MCU can only be in two modes: - under full software control - in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD allows the device to be used without any external RESET circuitry. HYSTERISIS VLVDhyst VLVDr VLVDf RESET 18/132 ST72141K 3.2 RESET MANAGER The RESET block includes three RESET sources as shown in Figure 11: s External RESET source pulse s Internal LVD RESET (Low Voltage Detection) s Internal WATCHDOG RESET The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. A 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles. Figure 11. Reset Block Diagram V DD fCPU COUNTER INTERNAL RESET RON RESET WATCHDOG RESET LVD RESET 19/132 ST72141K RESET MANAGER (Cont'd) External RESET pin The RESET pin is both an input and an open-drain output with integrated R ON weak pull-up resistor (see Figure 11). This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. A RESET signal originating from an external source must have a duration of at least tPULSE in order to be recognized. Two RESET sequences can be associated with this RESET source as shown in Figure 12. When the RESET is generated by a internal source, during the two first phases of the RESET sequence, the device RESET pin acts as an output that is pulled low. Generic Power On RESET The function of the POR circuit consists of waking up the MCU by detecting (at around 2V) a dynamic (rising edge) variation of the VDD Supply. At the beginning of this sequence, the MCU is configured in the RESET state. When the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal 4096 CPU cycles delay is initiated, in order to allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence is executed immediately following the internal delay. To ensure correct start-up, the user should take care that the VDD Supply is stabilized at a sufficient level for the chosen frequency (see Electrical Characteristics) before the reset signal is released. In addition, supply rising must start from 0V. As a consequence, the POR does not allow to supervise static, slowly rising, or falling, or noisy (oscillating) VDD supplies. An external RC network connected to the RESET pin, or the LVD reset can be used instead to get the best performance. Figure 12. External RESET Sequences VDD VDD nominal VLVDf RESET RUN DELAY tPULSE INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR RUN EXTERNAL RESET SOURCE RESET PIN WATCHDOG RESET 20/132 ST72141K RESET MANAGER (Cont'd) Internal Low Voltage Detection RESET (option) Two different RESET sequences caused by the internal LVD circuitry can be distinguished: - LVD Power-On RESET - Voltage Drop RESET Figure 13. LVD RESET Sequences VDDnominal VLVDr VDD In the second sequence, a "delay" phase is used to keep the device in RESET state until VDD rises up to VLVDr (see Figure 13). LVD POWER-ON RESET POWEROFF RESET INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR RUN EXTERNAL RESET SOURCE RESET PIN WATCHDOG RESET VDD VDDnominal VLVDr VLVDf RESET RUN DELAY VOLTAGE DROP RESET INTERNAL RESET FETCH 4096 CLOCK CYCLES VECTOR RUN EXTERNAL RESET SOURCE RESET PIN WATCHDOG RESET 21/132 ST72141K RESET MANAGER (Cont'd) Internal Watchdog RESET The RESET sequence generated by a internal Watchdog counter overflow has the shortest reset phase (see Figure 14). Figure 14. Watchdog RESET Sequence VDD VDDnominal VLVDf RESET RUN INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR RUN EXTERNAL RESET SOURCE tWDGRST RESET PIN WATCHDOG RESET WATCHDOG UNDERFLOW 22/132 ST72141K 3.3 LOW CONSUMPTION OSCILLATOR The main clock of the ST7 can be generated by two different sources: s an external source s a crystal or ceramic resonator oscillators External Clock Source In this mode, a square clock signal with ~50% duty cycle has to drive the OSC2 pin while the OSC1 pin is tied to V SS (see Figure 15). Crystal/Ceramic Oscillators This oscillator (based on constant current source) is optimized in terms of consumption and has the advantage of producing a very accurate rate on the main clock of the ST7. When using this oscillator, the resonator and the load capacitances have to be connected as shown in Figure 16 and have to be mounted as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. This oscillator is not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Figure 15. External Clock Figure 16. Crystal/Ceramic Resonator ST7 OSC1 OSC2 OSC1 ST7 OSC2 EXTERNAL SOURCE CL0 LOAD CAPACITANCES CL1 23/132 ST72141K 3.4 MAIN CLOCK CONTROLLER (MCC) The MCC block supplies the clock for the ST7 CPU and its internal peripherals. It allows the SLOW power saving mode and the Motor Contral and SPI peripheral clocks to be managed independently. The MCC functionality is controlled by two bits of the MISCR register: SMS and XT16. The XT16 bit acts on the clock of the motor control and SPI peripherals while the SMS bit acts on the CPU and the other peripherals. Figure 17. Main Clock Controller (MCC) Block Diagram OSC2 OSCILLATOR OSC1 MCC fOSC DIV 2 DIV 16 fCPU CPU CLOCK TO CPU AND PERIPHERALS XT16 - - - - - - SMS MISCR DIV 2 4MHz MOTOR CONTROL PERIPHERAL DIV 2 4MHz SPI PERIPHERAL 24/132 ST72141K 4 INTERRUPTS The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 18. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - The I bit of the CC register is set to prevent additional interrupts. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the "Exit from HALT" column in the Interrupt Mapping Table). 4.1 NON MASKABLE SOFTWARE INTERRUPT This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 18. 4.2 EXTERNAL INTERRUPTS External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically NANDed before entering the edge/level detection block. Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity. 4.3 PERIPHERAL INTERRUPTS Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: - The I bit of the CC register is cleared. - The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: - Writing "0" to the corresponding bit in the status register or - Access to the status register while the flag is set followed by a read or write of an associated register. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed. 25/132 ST72141K INTERRUPTS (Cont'd) Figure 18. Interrupt Processing Flowchart FROM RESET I BIT SET? Y N N INTERRUPT PENDING? Y FETCH NEXT INSTRUCTION N IRET? Y STACK PC, X, A, CC SET I BIT LOAD PC FROM INTERRUPT VECTOR EXECUTE INSTRUCTION RESTORE PC, X, A, CC FROM STACK THIS CLEARS I BIT BY DEFAULT 26/132 ST72141K INTERRUPTS (Cont'd) Table 4. Interrupt Mapping N Source Block RESET TRAP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 SPI TIMER A TIMER B MTC EI0 EI1 Reset Software Interrupt Not used External Interrupt Port A7..0 (C5..0*) External Interrupt Port B7..0 (C5..0*) Motor Control Interrupt (events: R, Z) Motor Control Interrupt (events: C, D) Motor Control Interrupt (events: E, O) SPI Peripheral Interrupts TIMER A Peripheral Interrupts TIMER B Peripheral Interrupts Not used Not used Not used Not Used Not Used Lowest Priority SPISR TASR TBSR MISR N/A yes yes no no no no no no Description Register Label N/A Priority Order Highest Priority Exit from HALT yes no Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFFAh-FFFBh FFF8h-FFF9h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h 27/132 ST72141K 5 POWER SAVING MODES 5.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, three main power saving modes are implemented in the ST7 (see Figure 19). After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f CPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the the oscillator status. Figure 19. Power saving mode consumption / transitions HALT Low POWER CONSUMPTION SLOW WAIT WAIT SLOW RUN High 28/132 ST72141K POWER SAVING MODES (Cont'd) 5.2 HALT Mode The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ST7 HALT instruction (see Figure 21). The MCU can exit HALT mode on reception of either an external interrupt or a reset (see Table 2). When exiting HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see Figure 20). Figure 20. HALT Mode timing overview RUN HALT 4096 CPU CYCLE DELAY RUN When entering HALT mode, the I bit in the CC Register is forced to 0 to enable interrupts. In the HALT mode the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). HALT INSTRUCTION RESET OR INTERRUPT FETCH VECTOR Figure 21. HALT modes flow-chart N HALT OSCILLATOR PERIPHERALS CPU I BIT OFF OFF OFF 0 WATCHDOG ENABLE Y HALT INSTRUCTION N RESET Y 4096 clock cycles delay N EXTERNAL* INTERRUPT OSCILLATOR PERIPHERALS CPU ON OFF OFF OSCILLATOR PERIPHERALS CPU ON ON ON Y FETCH RESET VECTOR OR SERVICE INTERRUPT** Notes: * External interrupt or internal interrupts with Exit from Halt Mode capability ** Before servicing an interrupt, the CC register is pushed on the stack. 29/132 ST72141K POWER SAVING MODES (Cont'd) 5.3 WAIT Mode WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the "WFI" ST7 software instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register are forced to 0, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 22. Figure 22. WAIT mode flow-chart 5.4 SLOW Mode This mode has two targets: - To reduce power consumption by decreasing the internal clock in the device, - To adapt the internal clock frequency (fCPU) to the available supply voltage. SLOW mode is controlled by the SMS bit in the MISCR register. This bit enables or disables Slow mode selecting the internal slow frequency (fCPU). In this mode, the oscillator frequency can be divided by 32 instead of 2 in normal operating mode. The CPU and peripherals are clocked at this lower frequency except the Motor Control and the SPI peripherals which have their own clock selection bit (XT16) in the MISCR register. WFI INSTRUCTION OSCILLATOR PERIPHERALS CPU I BIT ON ON OFF 0 N RESET Y if exit caused by a RESET, a 4096 CPU clock cycle delay is inserted. N INTERRUPT Y OSCILLATOR PERIPHERALS CPU ON OFF* OFF OSCILLATOR PERIPHERALS CPU ON ON ON FETCH RESET VECTOR OR SERVICE INTERRUPT** Note: * The peripheral clock is stopped only when exit caused by RESET and not by an interrupt. ** Before servicing an interrupt, the CC register is pushed on the stack. 30/132 ST72141K 6 I/O PORTS 6.1 INTRODUCTION The I/O ports offer different functional modes: - transfer of data through digital inputs and outputs and for specific pins: - external interrupt generation - alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 6.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: - Data Register (DR) - Data Direction Register (DDR) and one optional register: - Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 23 6.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Miscellaneous register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Figure 24). The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellaneous register must be modified. 6.2.2 Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status: DR 0 1 Push-pull VSS VDD Open-drain Vss Floating 6.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. 31/132 ST72141K I/O PORTS (Cont'd) Figure 23. I/O Port General Block Diagram REGISTER ACCESS ALTERNATE OUTPUT 1 VDD 0 ALTERNATE ENABLE DR P-BUFFER (see table below) PULL-UP (see table below) VDD DDR PULL-UP CONFIGURATION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below) PAD OR EXTERNAL INTERRUPT SOURCE (eix) Table 5. I/O Port Mode Options Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS Output Legend: NI - not implemented Off - implemented not activated On - implemented and activated 32/132 DATA BUS DR SEL 1 0 ALTERNATE INPUT FROM OTHER BITS POLARITY SELECTION NI (see note) Note: The diode to V DD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress. ST72141K I/O PORTS (Cont'd) Table 6. I/O Port Configurations Hardware Configuration NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONFIGURATION DR REGISTER ACCESS DR REGISTER W DATA BUS R INPUT 1) ALTERNATE INPUT FROM OTHER PINS INTERRUPT CONFIGURATION POLARITY SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS EXTERNAL INTERRUPT SOURCE (eix) OPEN-DRAIN OUTPUT 2) VDD RPU DR REGISTER ACCESS PAD DR REGISTER R/W DATA BUS ALTERNATE ENABLE ALTERNATE OUTPUT PUSH-PULL OUTPUT 2) NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU DR REGISTER ACCESS PAD DR REGISTER R/W DATA BUS ALTERNATE ENABLE ALTERNATE OUTPUT Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content. 33/132 ST72141K I/O PORTS (Cont'd) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings. 6.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 24 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 24. Interrupt I/O Port State Transitions 01 INPUT floating/pull-up interrupt 00 INPUT floating (reset state) 10 OUTPUT open-drain 11 OUTPUT push-pull XX = DDR, OR The I/O port register configurations are summarized as follows. 34/132 ST72141K I/O PORTS (Cont'd) Interrupt Ports PA7:0, PB5:3 (with pull-up) MODE floating input pull-up interrupt input open drain output push-pull output DDR 0 0 1 1 OR 0 1 0 1 True Open Drain Interrupt Ports PB2:0 (without pull-up) MODE floating input floating interrupt input true open drain (high sink ports) DDR 0 0 1 OR 0 1 X Table 7. Port Configuration Input Port Port A Port B Pin name OR = 0 PA7:0 PB5:3 PB2:0 floating floating floating OR = 1 pull-up interrupt pull-up interrupt floating interrupt OR = 0 OR = 1 open drain push-pull open drain push-pull true open drain Output 35/132 ST72141K I/O PORTS (Cont'd) 6.3.1 Register Description DATA REGISTER (DR) Port x Data Register PxDR with x = A or B. Read /Write Reset Value: 0000 0000 (00h) 7 D7 D6 D5 D4 D3 D2 D1 0 D0 OPTION REGISTER (OR) Port x Option Register PxOR with x = A or B. Read /Write Reset Value: 0000 0000 (00h) 7 O7 O6 O5 O4 O3 O2 O1 0 O0 Bit 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A or B. Read /Write Reset Value: 0000 0000 (00h) 7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0 Bit 7:0 = O[7:0] Option register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: floating input 1: pull-up input with or without interrupt Output mode: 0: output open drain (with P-Buffer unactivated) 1: output push-pull (when available) Bit 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode 36/132 ST72141K I/O PORTS (Cont'd) Table 8. I/O Port Register Map and Reset Values Address (Hex.) Register Label 7 6 5 4 3 2 1 0 Reset Value of all IO port registers 0000h 0001h 0002h 0004h 0005h 0006h PADR PADDR PAOR PBDR PBDDR PBOR 0 0 0 0 0 0 0 0 MSB LSB MSB LSB 37/132 ST72141K 7 MISCELLANEOUS REGISTER The miscellaneous register allows control over several different features such as the external interrupts or the I/O alternate functions. 7.1 I/O Port Interrupt Sensitivity Description The external interrupt sensitivity is controlled by the ISxx bits of the Miscellaneous register. This control allows to have two fully independent external interrupt source sensitivities as shown in Figure 25. Each external interrupt source can be generated on four different events on the pin: s Falling edge s Rising edge s Falling and rising edge s Falling edge and low level To guaranty correct functionality, a modification of the sensitivity in the MISCR register must be done only when the I bit of the CC register is set to 1 (interrupt masked). See I/O port register and Miscellaneous register descriptions for more details on the programming. Figure 25. External Interrupt Sensitivity MISCR IS01 IS00 EI0 INTERRUPT SOURCE 7.2 I/O Port Alternate Functions The MISCR register manages the SPI SS pin alternate function configuration. This makes it possible to use the PB2 I/O port function while the SPI is active. These functions are described in detail in Section 7.4 Miscellaneous Register Description. 7.3 Clock Prescaler Selection The MISCR register is used to select the SLOW mode (see Section 5.4 SLOW Mode for more details) and the SPI and Motor Control peripheral clock prescaler. PA7 SENSITIVITY CONTROL PA0 MISCR IS11 IS10 EI1 INTERRUPT SOURCE PB7 SENSITIVITY CONTROL PB0 38/132 ST72141K MISCELLANEOUS REGISTER (Cont'd) 7.4 Miscellaneous Register Description MISCELLANEOUS REGISTER (MISCR) Read /Write Reset Value: 0000 0000 (00h) 7 XT16 SSM SSI IS11 IS10 IS01 IS00 0 SMS 0 0 1 0 1 Falling edge & low level Rising edge only Falling edge only Rising and falling edge 0 1 1 Bits 4:3 = IS1[1:0] EI1 sensitivity The interrupt sensitivity defined using the IS1[1:0] bits combination is applied to the EI1 external interrupts. These two bits can be written only when the I bit of the CC register is set to 1 (interrupt masked). EI1: Port B IS11 IS10 External Interrupt Sensitivity Bit 7 = XT16 MTC and SPI clock selection This bit is set and cleared by software. The maximum allowed frequency is 4MHz. 0: MTC and SPI clock supplied with fOSC/2 1: MTC and SPI clock supplied with fOSC/4 Bit 6 = SSM SS mode selection This bit is set and cleared by software. 0: Normal mode - the level of the SPI SS signal is the external SS pin. 1: I/O mode, the level of the SPI SS signal is read from the SSI bit. Bit 5 = SSI SS internal mode This bit replaces the SS pin of the SPI when the SSM bit is set to 1. (see SPI description). It is set and cleared by software. Bits 2:1 = IS0[1:0] EI0 sensitivity The interrupt sensitivity defined using the IS0[1:0] bits combination is applied to the EI1 external interrupts. These two bits can be written only when the I bit of the CC register is set to 1 (interrupt masked). EI0: Port A IS01 IS00 0 0 1 1 0 1 0 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge Bit 0 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC / 2 1: Slow mode. fCPU = fOSC / 32 See sections on low power consumption mode and MCC for more details. Table 9. Miscellaneous Register Map and Reset Values Address (Hex.) 0020h Register Label MISCR Reset Value 7 XT16 0 6 SSM 0 5 SSI 0 4 IS11 0 3 IS10 0 2 IS01 0 1 IS00 0 0 SMS 0 39/132 ST72141K 8 ON-CHIP PERIPHERALS 8.1 MOTOR CONTROLLER (MTC) 8.1.1 Introduction The ST7 Motor Controller (MTC) can be seen as a Pulse Width Modulator multiplexed on six output channels, and a Back Electromotive Force (BEMF) zero-crossing detector for sensorless control of Permanent Magnet Direct Current (PMDC) brushless motors. The MTC is particularly suited to driving synchronous motors and supports operating modes like: - Commutation step control with motor voltage regulation and current limitation - Commutation step control with motor current regulation, i.e. direct torque control - Sensor or sensorless motor phase commutation control - BEMF zero-crossing detection with high sensitivity. The integrated phase voltage comparator is directly referred to the full BEMF voltage without any attenuation. A BEMF voltage down to 200 mV can be detected, providing high noise immunity and self-commutated operation in a large speed range. - Realtime motor winding demagnetization detection for fine-tuning the phase voltage masking time to be applied before BEMF monitoring. - Automatic and programmable delay between BEMF zero-crossing detection and motor phase commutation. 8.1.2 Main Features s Two on-chip analog comparators, one for BEMF zero-crossing detection with 100 mV hysteresis, the other for current regulation or limitation s Four selectable reference voltages for the hysteresis comparator (0.2 V, 0.6 V, 1.2 V, 2.5 V) s 8-bit timer (MTIM) with two compare registers and two capture features s Measurement window generator for BEMF zero-crossing detection s Auto-calibrated prescaler with 16 division steps s 8x8-bit multiplier s Phase input multiplexer s Sophisticated output management: - The six output channels can be split into two groups (odd & even). - The PWM signal can be multiplexed on even, odd or both groups, alternatively or simultaneously. - The output polarity is programmable channel by channel. - An software enabled bit (active low) forces the outputs in HiZ. - An "emergency stop" input pin (active low) asynchronously forces the outputs in HiZ. Table 10. MTC Registers Register MTIM MZPRV MZREG MCOMP MDREG MWGHT MPRSR MIMR MISR MCRA MCRB MPHST MPAR MPOL Description Timer Counter Register Capture Zn-1 Register Capture Zn Register Compare Cn+1 Register Demagnetization Register An Weight Register Prescaler & Sampling Register Interrupt Mask Register Interrupt Status Register Control Register A Control Register B Phase State Register Parity Register Polarity Register Page 67 67 67 67 67 67 67 68 68 69 70 71 71 71 8.1.3 Application Example This example shows a six-step command sequence for a 3-phase permanent magnet DC brushless motor (PMDC motor). Figure 27 shows the phase steps and voltage, while Table 11 shows the relevant phase configurations. To run this kind of motor efficiently, an autoswitching mode has to be used, i.e. the position of the rotor must self-generate the powered winding commutation. The BEMF zero crossing (Z event) on the non-excited winding is used by the MTC as a rotor position sensor. The delay between this event and the commutation is computed by the MTC and the commutation event Cn is automatically generated after this delay. After the commutation occurs, the MTC waits until the winding is completely demagnetized by the free-wheeling diode: during this phase the winding is tied to 0V or to the HV high voltage rail and no BEMF can be read. At the end of this phase a new BEMF zero-crossing detection is enabled. The end of demagnetization event (D), is also detected by the MTC or simulated with a timer compare feature when no detection is possible. 40/132 ST72141K MOTOR CONTROLLER (Cont'd) The MTC manages these three events always in the same order: Z generates C after a delay computed in realtime, then waits for D in order to enable the peripheral to detect another Z event. The speed regulation is managed by the microcontroller, by means of an adjustable reference current level in case of current control, or by direct PWM duty-cycle adjustment in case of voltage control. All detections of Zn events are done during a short measurement window while the high side switch is turned off. For this reason the PWM signal is applied on the high side switches. When the high side switch is off, the high side winding is tied to 0V by the free-wheeling diode, the low side winding voltage is also held at 0V by the low side ON switch and the complete BEMF voltage is present on the third winding: detection is then possible. Figure 26. Chronogram of Events (in Autoswitched Mode) C event Z event DH event DS event Cn processing Wait for Cn Wait for Dn Wait for Z T Zn Dn Cn Z > Zn min C > Cn min t Voltage on phase A Voltage on phase B Voltage on phase C BEMF sampling P signal when sampled (Output of the V DD analog MUX) VREF (Threshold value for VSS Input comparator) 41/132 ST72141K MOTOR CONTROLLER (Cont'd) Figure 27. Example of Command Sequence for 6-step Mode (typical 3-phase PMDC Motor Control) Step Switch 0 1 I1 2 3 I3 4 5 Node A HV HV/2 0 1 2 3 4 5 6 1 2 3 HV T0 T2 B I6 T4 I4 A I5 I2 C T3 T5 T1 B HV HV/2 0 HV HV/2 0 C Note: Control & sampling PWM influence is not represented on these simplified chronograms. 1 2 3 4 5 HV 6 C2 D2 HV/2 C4 Superimposed voltage (BEMF induced by rotor) - approx. HV/2 (PWM on) - approx. 0V (PWM off) 0V Z2 Demagnetization Commutation delay D 5 Z5 t PWM off pulses Wait for BEMF = 0 42/132 ST72141K MOTOR CONTROLLER (Cont'd) Table 11. Step Configuration Summary Configuration BEMF BEMF Phase state edge input register Current direction High side Low side OO[5:0] bits in MPHST register Measurement done on: IS[1:0] bits in MPHST register Back EMF shape CPB bit in MCRB register (ZVD bit = 0) Voltage on measured point at the start of demagnetization Step 1 A to B T0 T5 100001 MCIC 10 Falling 0 0V 2 A to C T0 T1 000011 MCIB 01 Rising 1 HV 3 B to C T2 T1 000110 MCIA 00 Falling 0 0V 4 B to A T2 T3 001100 MCIC 10 Rising 1 HV 5 C to A T4 T3 011000 MCIB 01 Falling 0 0V 6 C to B T4 T5 110000 MCIA 00 Rising 1 HV Hardware-software demagnetization Hardware or HDM-SDM bits in MCRB register 10 11 10 11 10 11 Demagnetization PWM side selection to accelerate Odd Side Even Side Odd Side Even Side Odd Side Even Side demagnetization switch Driver selection to accelerate demagnetization T5 T0 T1 T2 T3 T4 For a detailed description of the MTC registers, see Section 8.1.7. 43/132 ST72141K MOTOR CONTROLLER (Cont'd) 8.1.4 Functional Description The MTC can be split into four main parts as shown in the simplified block diagram in Figure 28. - The BEMF ZERO-CROSSING DETECTOR with a comparator and an input multiplexer. - The DELAY MANAGER with an 8-bit timer (MTIM) and an 8x8 bit multiplier. - The PWM MANAGER, including a measurement window generator, a mode selector and a current comparator. Figure 28. Simplified MTC Block Diagram - The CHANNEL MANAGER with the PWM multiplexer, polarity programming capability and emergency HiZ configuration input. 8.1.4.1 Input Detection Block This block can operate in sensor mode or sensorless mode. The mode is selected via the SR bit in the MCRA register. The block diagram is shown in Figure 29. DELAY MANAGER DELAY WEIGHT CAPTURE Zn MTIM TIMER BEMF ZERO-CROSSING DETECTOR BEMF=0 [Z] MCIA MCIB MCIC Internal VREF DELAY = WEIGHT x Zn =? COMMUTE [C] MCO5 PHASE MEASUREMENT WINDOW GENERATOR (I) CURRENT VOLTAGE (V) (I) (V) MODE NMCES PWM (1) (V) (I) VDD MCCFI OCP1A MCO4 MCO3 MCO2 MCO1 MCO0 PWM MANAGER Note 1: The PWM signal is generated by the ST7 16-bit Timer [Z] : Back EMF Zero-crossing event Zn : Time elapsed between two consecutive Z events [C] : Commutation event Cn : Time delayed after Z event to generate C event (I): Current mode (V): Voltage mode CHANNEL MANAGER R1ext (V) R2ext Cext (I) 44/132 ST72141K MOTOR CONTROLLER (Cont'd) Input Pins The MCIA, MCIB and MCIC input pins can be used as analog pins in Sensorless mode or as digital pins in Sensor mode. In sensorless mode, the analog inputs are used to measure the BEMF zero crossing and to detect the end of demagnetization if required. In Sensor mode, they are connected to sensor outputs. Due to the presence of diodes, these pins can permanently support an input current of 5 mA. In Sensorless mode, this feature enables the inputs to be Figure 29. Input Stage External Input Block Input Comparator Block MPHST Register Inputn Sel Reg MCIA A MCIB B MCIC C 00 C P + DQ connected to each motor phase through a single resistor. Note: In high voltage applications, in Sensorless mode and for certain motors and power topologies (with parasitic capacitance or other), it may be required to add external pull-up Schottky 0.4 V (e.g. BAT48) diodes on the MCIA, MCIB and MCIC pins. A multiplexer, programmed by the IS[1:0] bits in MPHST register selects the input pins and connects them to the rotor position control logic in either Sensorless or Sensor mode. Event Detection IS[1:0] 01 Sample CP 10 VREF 2 DS,H C 1 MCRB Register VR[1:0] Freq (T=1.25s) for demagnetization and sensors Sampling frequency 16-bit Timer PWM Notes: Reg Regn I V C Z DS,H E R O 1 I V MCRA Register V0C1 bit Updated/Shifted on R Updated with Regn+1 on C * = Preload register, changes taken into account at next C event. MPAR Register DS,H C Sample 2 MCRB Register MPAR Register CPBn bit* ZVD bit 20 s / D or or or Current Mode Voltage Mode events: Commutation BEFM Zero-crossing End Of Demagnetization Emergency Stop Ratio Updated (+1 or -1) Multiplier Overflow Branch taken after C event Branch taken after D event REO bit Z 20s / C 1 or MCRA Register SR bit DH +/- 2 CPBn bit* HDMn bit* MCRB Register 45/132 ST72141K MOTOR CONTROLLER (Cont'd) Sensorless Mode This mode is used to detect BEMF zero crossing and end of demagnetization events. The analog phase multiplexer connects the nonexcited motor winding to an analog 100mV hysteresis comparator referred to a selectable reference voltage. The VR[1:0] bits in the MCRB register select the reference voltage from four internal values depending on the noise level and the application voltage supply. BEMF detections are performed during the measurement window, when the excited windings are free-wheeling through the low side switches and diodes. At this stage the common star connection voltage is near to ground voltage (instead of V DD/2 when the excited windings are powered) and the complete BEMF voltage is present on the non-excited winding terminal, referred to the ground terminal. The zero crossing sampling frequency is then defined, in current mode, by the measurement window generator frequency (SA[3:0] bits in the MPRSR register) or, in voltage mode, by the 16-bit Timer PWM frequency and duty cycle. Table 12. ZVD and CPB Edge Selection Bits ZVD bit CPB bit 20-s filter 0 0 Event generation vs input data sampled 20-s filter During a short period after a phase commutation (C event), the winding is no longer excited but needs a demagnetisation phase during which the BEMF cannot be read. A demagnetization current goes through the free-wheeling diodes and the winding voltage is stuck at the high voltage or to the ground terminal. For this reason an "end of demagnetization event" D must be detected on the winding before the detector can sense a BEMF zero crossing. For the end-of-demagnetization detection, no special PWM configuration is needed, the comparator sensing is done at a fixed 800kHz sampling frequency. So, the three events: C (commutation), D (demagnetization) and Z (BEMF zero crossing) must always occur in this order. The comparator output is processed by a detector that automatically recognizes the D or Z event, depending on the CPB or ZVD edge and level configuration bits as described in Table 12. A 20-s filter after a C event disables a D event if spurious spikes occur. Another 20-s filter after a D event disables a Z event if spurious spikes occur. C 20-s filter 0 1 DH 20-s filter Z C 20-s filter 1 0 DH 20-s filter Z C 20-s filter 1 1 DH 20-s filter Z C DH Z Note: The ZVD bit is located in the MPAR register, the CPB bit is in the MCRB register. 46/132 ST72141K MOTOR CONTROLLER (Cont'd) Demagnetization (D) Event At the end of the demagnetization phase, current no longer goes through the free-wheeling diodes. The voltage on the non-excited winding terminal goes from one of the power rail voltages to the common star connection voltage plus the BEMF voltage. In some cases (if the BEMF voltage is positive and the free-wheeling diodes are at ground for example) this end of demagnetization can be seen as a voltage edge on the selected MCIx input and it is called a hardware demagnetization event D H. See Table 12. If enabled by the HDM bit in the MCRB register, the current value of the MTIM timer is captured in register MDREG when this event occurs in order to be able to simulate the demagnetization phase for the next steps. When enabled by the SDM bit in the MCRB register, demagnetization can also be simulated by comparing the MTIM timer with the MDREG register. This kind of demagnetization is called software demagnetization D S. If the HDM and SDM bits are both set, the first event that occurs, triggers a demagnetization event. For this to work correctly, a D S event must Figure 30. D Event Generation Mechanism DS,H C Sample 2 1 or not precede a DH event because the latter could be detected as a Z event. Software demagnetization can also be always used if the HDM bit is reset and the SDM bit is set. This mode works as a programmable masking time between the C and Z events. To drive the motor securely, the masking time must be always greater than the real demagnetization time in order to avoid a spurious Z event. When an event occurs, (either DH or DS) the DI bit in the MISR register is set and an interrupt request is generated if the DIM bit of register MIMR is set. Warning 1: Due to the alternate automatic capture and compare of the MTIM timer with MDREG register by DH and DS events, the MDREG register should be manipulated with special care. Warning 2: To avoid a system stop, the value written to the MDREG register in Soft Demagnetization Mode (SDM = 1) should always be: - Greater than the MCOMP value of the commutation before the related demagnetization - Greater than the value in the MTIM counter at that moment (when writing to the MDREG register). MTIM [8-bit Up Counter] 8 To Z event detection 20 s / C MCRA Register SR bit DH MDREG [Dn] Compare DH CPBn bit* HDM n bit* MCRB Register SDM bit 20s / C MCRB Register DS DH HDM bit SDM bit DS F(x) D = DH & HDM bit + DS & SDM bit D updated on R event * = Preload register, changes taken into account at next C event Register To interrupt generator 47/132 ST72141K MOTOR CONTROLLER (Cont'd) Table 13. Demagnetisation (D) Event Generation (example for ZVD=0) HDM bit Meaning CPB bit = 1 CPB bit = 0 (Even ) (Odd ) D = DS = Output Compare [MDREG, MTIM registers] Undershoot due to motor parasite or first sampling 2 HVV HV Weak / null undershoot and BEMF positive 2 HVV 5 DS C C Software Mode 0 (SDM bit =1 and HDM bit = 0) HV/2 DS (*) HV/2 DS C HV/2 (*) (*) 0V 0V 0V Z D = D H + DS Z Z D = DH (Hardware detection only) (Hardware detection or Output compare true) Undershoot due to Weak / null motor parasite or first undershoot and sampling BEMF positive 2 2 HV HV 5 HV C 1 Hardware/Simulated Mode (SDM bit = 1 and HDM bit = 1) HV/2 DS C (*) HV/2 DS C HV/2 (*) (*) 0V 0V 0V DH Z Z DH Z (*) Note: This is a zoom to the additional voltage induced by the rotor (Back EMF) 48/132 ST72141K MOTOR CONTROLLER (Cont'd) BEMF Zero Crossing (Z) Event When both C and D events have occurred, the PWM may be switched to another group of outputs (depending on the OS[2:0] bits in the MCRB register) and the real BEMF zero crossing sampling can start (see Figure 32). A BEMF voltage is present on the non-powered terminal but referred to common star connection of the motor whose voltage is equal to V DD/2. When a winding is free-wheeling (during PWM offtime) its terminal voltage changes to the other power rail voltage, that means if the PWM is applied on the high side driver, free-wheeling will be done through the high side diode and the terminal will be 0V. This is used to force the common star connection to 0V in order to read the BEMF referred to the ground terminal. Figure 31. Sampling and Zero Crossing Blocks Output of hysteresis comparator Freq. (T=1.25us) for Demagnetization and Sensor 1 Consequently, BEMF reading (i.e. comparison with a voltage close to 0V) can only be done when the PWM is applied on the high side drivers. For this reason the MTC outputs can be split in two groups called ODD and EVEN and the BEMF reading will be done only when PWM is applied on one of these two groups. The REO bit in the MPAR register is used to select the group to be used for BEMF sensing (high side group) Refer to Table 15 for an overview of when a BEMF can be read depending on REO bit, PWM mode and function mode of peripheral. Depending on the edge and level selection (ZVD and CPB) bits and when PWM is applied on the correct group, a BEMF zero crossing detection sets the ZI bit in the MISR register and generates an interrupt if the ZIM bit is set. The Z event also triggers some timer/multiplier operations, for more details see Section 8.1.4.2 Sample DQ C P Sampling frequency 16-bit Timer PWM Notes: Reg Regn I V C Z DS,H E R+/O 1 I V MCRA Register 2 DS,H C V0C1 bit Updated/Shifted on R Updated with Regn+1 on C MPAR Register DS,H C REO bit MCRB Register MPAR Register CPBn bit* ZVD bit 20s / D or or or Current M ode Voltage M ode events: Commutation BEFM Zero-crossing End Of Demagnetization Em ergency Stop Ratio Updated (+1 or -1) M ultiplier Overflow Branch taken after C event Branch taken after D event Sample 2 1 Z SR bit MCRA Register To D detection 2 * = Preload register, changes taken into account at next C event. 49/132 ST72141K MOTOR CONTROLLER (Cont'd) Sensor Mode In sensor mode, the rotor position information is given to the peripheral by means of logical data on the three inputs MCIA, MCIB and MCIC. For each step one of these three inputs is selected (IS[1:0] bits in register MPHST) in order to detect the Z event. In this case Demagnetization has no meaning and the relevant features such as the special PWM configuration, D S or DH management, 20-s filter; are not available (see Table 14). For this configuration the rotor detection doesn't need a particular phase configuration to validate the measurement and a Z event can be read from any detection window. A fixed sampling frequency (800 kHz) is used, that means the Z event and position sensoring is more precise than it is in sensorless mode. Table 14. Sensor mode selection SR bit 0 1 Mode Sensors not used Sensors used OS2 bit use Enabled Disabled Event detection sampling clock D: Clock 1.25s Z: SA&OT config. Z: Clock 1.25s Filtering 20s after C for D event 20s after D for Z event 20s after C for Z event Behaviour of the output PWM "Before D" behaviour & "after D" behaviour Only "after D" behaviour The minimum off time for current control PWM is also reduced to 1.25s. Procedure for reading sensor inputs in Direct Access mode: In Direct Access mode, the peripheral clock is disabled as shown in Table 25. As the data present on the selected input is synchronized by a 800 kHz clock, the sensor can't be read directly (the value is latched). To read the sensor data the following steps have to be performed: 1. Select the appropriate MCIx input pin by means of the IS[1:0] bits in the MPHST register 2. Switch from direct access mode to indirect access mode in order to latch the sensor data (DAC bit in MCRA register). 3. Switch back to direct access mode. 4. Read the comparator output (HST bit in the MIMR register) 50/132 ST72141K MOTOR CONTROLLER (Cont'd) Figure 32. Functional Diagram of Z Detection after D Event DS or DH Begin 20s Filter turned on Switch Sampling Clock[D] -> Sampling Clock[Z] Side change on Output PWM ? Yes No Change the side according to OS[2:0] Wait for next sampling clock edge Read enable by REO ? Yes No Filter off ? Yes Read enabled No End 51/132 ST72141K MOTOR CONTROLLER (Cont'd) Table 15. Modes permitting BEMF reading after Demagnetization (D event) SR bit (Sensor/ Demagnetization Sensorless Mode) V0C1 bit (Voltage/ Current Mode) OS[2:0] bits (PWM Output Config.) x00 REO bit Significant (Read PWM BEMF on Group Even/Odd group) Even 0 BEMF reading permitted after D event when: x01 1 x10 Odd 1 Even 0 x10 Odd 1 000 After D event Even 0 0 001 Odd 1 100 0 101 Even 0 Odd 1 110 Even 0 110 Odd Even and Odd Odd or Even 1 x 1 Not Used x x11 xxx x x Other cases Sensorless mode, Current Mode, PWM output only on Even group and BEMF read on Even group Sensorless mode, Current Mode, PWM output only on Odd group and BEMF read on Odd group Sensorless mode, Current Mode, PWM output on alternate groups but BEMF read only on Even group Sensorless mode, Current Mode, PWM output on alternate groups but BEMF read only on Odd group Sensorless mode, Voltage Mode, PWM output only on Even group and BEMF read on Even group Sensorless mode, Voltage Mode, PWM output only on Odd group and BEMF read on Odd group Sensorless mode, Voltage Mode, PWM output only on Even group and BEMF Read on Even group Sensorless mode, Voltage Mode, PWM output only on Odd group and BEMF Read on Odd group Sensorless mode, Voltage Mode, PWM output on alternate groups but BEMF read only on Even group Sensorless mode, Voltage Mode, PWM output on alternate groups but BEMF read on Odd group Sensorless mode, Current or Voltage Mode, PWM output on both groups, BEMF read on either group Sensor Mode, in any PWM output configuration, BEMF read on either group BEMF reading forbidden 52/132 ST72141K MOTOR CONTROLLER (Cont'd) 8.1.4.2 Delay Manager Figure 33. Overview of MTIM Timer Tratio ck 8-bit Up Counter MTIM 8 Z MZREG [Zn] Z MZPRV [Zn-1] DH MDREG [Dn] clr 1 0 MCRA register SWA bit Z C Compare MCRB register SDM bit MCOMP [Cn+1] 20s/C DS Compare C C DS,H To interrupt generator To interrupt generator To interrupt generator = Register updated on R event Z This part of the MTC contains all the time-related functions, its architecture is based on an 8-bit shift left/shift right timer shown in Figure 33. The MTIM timer includes: - An auto-updated prescaler - A capture/compare register for software demagnetization simulation (MDREG) - Two cascaded capture register (MZREG and MZPRV) for storing the times between two consecutive BEMF zero crossings (Z events) - An 8x8 bit multiplier for auto computing the next commutation time - One compare register for phase commutation generation (MCOMP) The MTIM timer module can work in two main modes. In switched mode the user must process the step duration and commutation time by software, in autoswitched mode the commutation action is performed automatically depending on the rotor position information and register contents. Table 16. Switched and Autoswitched Modes SWA bit 0 1 Commutation Type Switched mode Autoswitched mode MCOMP User access Read/Write Read only Switched Mode This feature allows the motor to be run step-bystep. This is useful when the rotor speed is still too low to generate a BEMF. It can also run other kinds of motor without BEMF generation such as induction motors or switch reluctance motors. This mode can also be used for autoswitching with all computation for the next commutation time done by software (hardware multiplier not used) and using the powerful interrupt set of the peripheral. In this mode, the step time is directly written by software in the commutation compare register MCOMP. When the MTIM timer reaches this value a commutation occurs (C event) and the MTIM timer is reset. 53/132 ST72141K MOTOR CONTROLLER (Cont'd) At this time all registers with a preload function are loaded (registers marked with (*) in Section 8.1.7). The CI bit of MISR is set and if the CIM bit in the MISR register is set an interrupt is generated. An overflow of the MTIM timer generates an RPI interrupt if the RIM bit is set. The MTIM timer prescaler (Step ratio bits ST[3:0] in the MPRSR register) is user programmable. Access to this register is not allowed while the MTIM timer is running (access is possible only before the starting the timer by means of the MOE bit) but the prescaler contents can be incremented/decremented at the next commutation event by setting the RMI (decrement) or RPI (increment) bits in the MISR register. When this method is used, at the next commutation event the prescaler value will be Table 17. Step Ratio Update MOE bit SWA bit Clock State 0 1 1 x 0 1 Disabled Enabled Enabled Always possible Read updated but also all the MTIM timer-related registers will be shifted in the appropriate direction to keep their value. After it has been taken into account, (at commutation) the RPI or RMI bit is reset. See Table 17. Only one update per step is allowed, so if both RPI and RMI are set together, RPI is taken into account at the next commutation and RMI is used one commutation latter. In switched mode, BEMF and demagnetization detection are already possible in order to pass in autoswitched mode as soon as possible but Z and D events do not affect the timer contents. Warning: In this mode, MCOMP must never be written to 0. Ratio Increment Ratio Decrement (Slow Down) (Speed-Up) Write the ST[3:0] value directly in the MPRSR register Set RPI bit in the MISR register Set RMI bit in the MISR register till next commutation till next commutation Automatically updated according to MZREG value 54/132 ST72141K MOTOR CONTROLLER (Cont'd) Figure 34. Step Ratio Functional Diagram 4MHz R+ +1 MPRSR Register MTIM Timer = FFh? 4 1 / 2Ratio Zn < 55h? RTratio ck 2 MHz - 62.5 Hz MTIM Timer control over Tratio and register operation 1/2 ST[3:0] Bits -1 MTIM Timer Overflow Z Capture with MTIM Timer Underflow (Zn < 55h) Begin Begin No Ratio < Fh? Ratio > 0? No Yes Ratio = Ratio + 1 Zn = Zn / 2 Zn+1 = Zn+1/2 Dn = Dn/2 Counter = Counter/2 Re-compute Cn Yes Ratio = Ratio - 1 Zn = Zn x 2 Zn+1 = Zn+1 x 2 Dn = Dn x 2 Counter = Counter x 2 Compute Cn End End Slow-down control Speed-up control 55/132 ST72141K MOTOR CONTROLLER (Cont'd) Autoswitched Mode In this mode the MCOMP register content is automatically computed in real time as described below and in Figure 35. This register is READ ONLY. The C event has no effect on the contents of the MTIM timer. When a Z event occurs the MTIM timer value is captured in the MZREG register, the previous captured value is shifted into the MZPRV register and the MTIM timer is reset. See Figure 26. One of these two registers (depending on the DCB bit in the MCRA register) is multiplied with the contents of the MWGHT register and divided by 32. The result is loaded in the MCOMP compare register, which automatically triggers the next commutation (C event) Table 18. Multiplier Result DCB bit 0 1 Commutation Delay MCOMP = MWGHT x MZPRV / 32 MCOMP = MWGHT x MZREG / 32 When an overflow occurs during the multiply operation, FFh is written in the MCOMP register and an interrupt (O event) is generated if enabled by the OIM bit in the MIMR register. Figure 35. Commutation Processor Block MZREG [Zn] Z MZPRV [Zn-1] MCRA Register DCB bit MWGHT [an+1] 8 A x B / 32 MCRA Register SWA bit 8 MCOMP [Cn+1] n-1 n 8 O To interrupt generator 3 set When the timer reaches this value an RPI interrupt is generated (timer overflow). After each shift operation the multiply is recomputed for greater precision. Using either the MZREG or MZPRV register depends on the motor symmetry and type. The MWGHT register gives directly the phase shift between the motor driven voltage and the BEMF. This parameter generally depends on the motor and on the speed. Auto-updated Step Ratio Register: In switched mode, the MTIM timer is driven by software only and any prescaler change has to be done by software (see Section 8.1.4.2 for more details). - In autoswitched mode an auto-updated prescaler always configures the MTIM timer for best accuracy. Figure 34 shows process of updating the Step Ratio bits: - When the MTIM timer value reaches FFh, the prescaler is automatically incremented in order to slow down the MTIM timer and avoid an overflow. To keep consistent values, the MTIM register and all the relevant registers are shifted right (divided by two). The RPI bit in the MISR register is set and an interrupt is generated (if RIM is set). - When a Z-event occurs, if the MTIM timer value is below 55h, the prescaler is automatically decremented in order to speed up the MTIM timer and keep precision better than 1.2%. The MTIM register and all the relevant registers are shifted left (multiplied by two). The RMI bit in the MISR register is set and an interrupt is generated if RIM is set. - If the prescaler contents reach the value 0, it can no longer be automatically decremented, the MTC continues working with the same prescaler value, i.e. with a lower accuracy. No RMI interrrupt can be generated. - If the prescaler contents reach the value 15, it can no longer be automatically incremented. When the timer reaches the value FFh, the prescaler and all the relevant registers remain unchanged and no interrupt is generated, the timer clock is disabled, and its contents stay at FFh The PWM is still generated and the D and Z detection circuitry still work, enabling the capture of the maximum timer value. The automatically updated registers are: MTIM, MZREG, MZPRV, MCOMP and MDREG. Access to these registers is summarised in Table 21. = Register updated on R event 56/132 ST72141K MOTOR CONTROLLER (Cont'd) Table 19. MTIM Timer-related Registers Name MTIM MZPRV MZREG MCOMP MDREG Reset Value 00h 00h 00h 00h 00h Contents Timer Value Capture Zn-1 Capture Zn Compare Cn+1 Demagnetization Dn These configuration bits are: CPB, HDM, SDM and OS2 in the MCRB register and IS[1:0], OO[5:0] in the MPHST register. Note on initializing the MTC: As shown in Table 21 all the MTIM timer registers are in read-write mode until the MTC clock is enabled (with the MOE and DAC bits). This allows the timer, prescaler and compare registers to be properly initialized for start-up. In sensorless mode, the motor has to be started in switched mode until a BEMF voltage is present on the inputs. This means the prescaler ST[3:0] bits and MCOMP register have to be modified by software. When running the ST[3:0] bits can only be incremented/decremented, so the initial value is very important. When starting directly in autoswitched mode (in sensor mode for example), write an appropriate value in the MZREG and MZPRV register to perform a step calculation as soon as the clock is enabled. Note on using the auto-updated MTIM timer: The auto-updated MTIM timer works accurately within its operating range but some care has to be taken when processing timer-dependent data such as the step duration for regulation or demagnetization. For example if an overflow occurs when calculating a software end of demagnetization (MCOMP+demagnetisation_time>FFh), the value that stored in MDREG will be: 7Fh+(MCOMP+demagnetization_time-FFh)/2. Note on commutation interrupts: It is good practice to modify the configuration for the next step as soon as possible, i.e within the commutation interrupt routine. All registers that need to be changed at each step have a preload register that enables the modifications for a complete new configuration to be performed at the same time (at C event in normal mode or when writing the MPHST register in direct access mode). 57/132 ST72141K MOTOR CONTROLLER (Cont'd) The Figure 36 gives the step ratio register value (left axis) and the number of BEMF sampling during one electrical step with the corresponding accuracy on the measure (right axis) as a function of the mechanical frequency. For a given prescaler value (step ratio register) the mechanical frequency can vary between two fixed values shown on the graph as the segment ends. In autoswitched mode, this register is automatically incremented/decremented when the step frequency goes out of this segment. At fcpu=4MHz, the range covered by the Step Ratio mechanism goes from 2.39 to 235000 (pole pair x rpm) with a minimum accuracy of 1.2% on the step period. To read the number of samples for Zn within one step (right Y axis), select the mechanical frequency on the X axis and the sampling frequency curve used for BEMF detection (PWM frequency or measurment window frequency). For example, for N.Frpm = 15,000 and a sampling frequency of 20kHz, there are approximately 10 samples in one step and there is a 10% error rate on the measurement. Figure 36. Step Ratio Bits decoding and accuracy results and BEMF Sampling Rate avg Zn ~ 55h 1.2% ST[3:0] Step Ratio (Decimal) avg Zn ~ 7Fh 0.6% avg Zn ~ FFh 0.4% BEMF samples Zn/Zn 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 avg Zn ~ FFh 0.4% Fn Fn+1 = 2.Fn 1 100% avg Zn ~ 55h 1.2% 200 Hz 20 kHz 3.Fn+1 = 6.Fn avg Zn ~ 7Fh 0.6% 3.Fn 2 50% 4 10 10% 0% N.Frpm 76.6 115 153 230 306 460 614 920 1230 1840 2450 3680 4900 7350 9800 14700 19600 29400 39200 58800 78400 118000 1 157000 235000 2.39 4.79 7.18 9.57 14.4 19.1 28.7 38.3 57.4 Fstep = 6.N.Frpm = N.F / 10 N.F = 10.Fstep Fstep: Electrical step frequency N: Pole pair number 58/132 ST72141K MOTOR CONTROLLER (Cont'd) Table 20. Step Frequency/Period Range Step Ratio Bits ST[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Maximum Step Frequency 23.5 kHz 11.7 kHz 5.88 kHz 2.94 kHz 1.47 kHz 735 Hz 367 Hz 183 Hz 91.9 Hz 45.9 Hz 22.9 Hz 11.4 Hz 5.74 Hz 2.87 Hz 1.43 Hz 0.718 Hz Minimum Step Frequency 7.85 kHz 3.93 kHz 1.96 kHz 980 Hz 490 Hz 245 Hz 123 Hz 61.3 Hz 30.7 Hz 15.4 Hz 7.66 Hz 3.83 Hz 1.92 Hz 0.958 Hz 0.479 Hz 0.240 Hz Minimum Step Period 42.5 s 85 s 170 s 340 s 680 s 1.36 ms 2.72 ms 5.44 ms 10.9 ms 21.8 ms 43.6 ms 87 ms 174 ms 349 ms 697 ms 1.40 s Maximum Step Period 127.5 s 255 s 510 s 1.02 ms 2.04 ms 4.08 ms 8.16 ms 16.32 ms 32.6 ms 65.2 ms 130 ms 261 ms 522 ms 1.04 s 2.08 s 4.17 s Table 21. Modes of Accessing MTIM Timer-Related Registers RST bit 0 State of MCRA Register Bits SWA bit MOE bit Mode 0 0 Configuration Mode Access to MTIM Timer Related Registers Read Only Access Read / Write Access MTIM, MZPRV, MZREG, MCOMP, MDREG, ST[3:0] MCOMP, MDREG, MTIM, MZPRV, MZREG, ST[3:0] RMI bit of MISR: 0: No action 1: Decrement ST[3:0] RPI bit of MISR: 0: No action 1: Increment ST[3:0] MTIM, MZPRV, MZREG, MCOMP, MDREG, ST[3:0] MDREG,RMI, RPI bit of MISR: Set by hardware, (increment ST[3:0]) Cleared by software 0 0 1 Switched Mode 0 0 1 1 0 1 Emergency Stop Autoswitched Mode MTIM, MZPRV, MZREG, MCOMP, ST[3:0] 59/132 ST72141K MOTOR CONTROLLER (Cont'd) 8.1.4.3 PWM Manager The PWM manager controls the motor via the six output channels in voltage mode or current mode depending on the V0C1 bit in the MCRA register. A block diagram of this part is given in Figure 37. Voltage Mode In Voltage mode (V0C1 bit = "0"), the PWM is generated by the 16-bit A Timer. Its duty cycle is programmed by software (refer to the chapter on the 16-bit Timer) as required by the application (speed regulation for example). The current comparator is used for safety purposes as a current limitation. For this feature, the detected current must be present on the MCCFI pin and the current limitation must be present on pin OCP1A. This current limitation is fixed by a voltage reference depending on the maximum current acceptable for the motor. This current limitation is generated with the V DD voltage by means of an external divider but can also be adjusted with an external reference voltage ( 3.7 V). The external components are adjusted by the user depending on the application needs. In Voltage mode, it is mandatory to set a current limitation. In sensorless mode the BEMF zero crossing is done during the PWM off time. Figure 37. Current Feedback The PWM signal is directed to the channel manager that connects it to the programmed outputs (See Figure 39). Current Mode In current mode, the PWM output signal is generated by a combination of the output of the measurement window generator (see Figure 38) and the output of the current comparator, and is directed to the output channel manager as well (Figure 39). The current reference is provided to the comparator by the PWM output of the 16-bit Timer (0.25% accuracy), filtered through a RC filter (external capacitor on pin OCP1A and an internal voltage divider 30K and 70K). The detected current input must be present on the MCCFI pin. To avoid spurious commutations due to parasitic noise after switching on the PWM, a 2.5-s filter can be applied on the comparator output by setting the CFF bit in the MCRB register. The On state of the resulting PWM starts at the end of the measurement window (rising edge), and ends either at the beginning of the next measurement window (falling edge), or when the current level is reached. 16-bit Timer - PWM MCRA Register V0C1 bit (V) VDD R1ext (I) MCCFI OCP1A (V) C EXT R2ext + VCREF (I) R1 R2 MCRA Register CFF bit Sampling frequency 2.5-s Filter To Phase State Control Common Mode = VDD - (1,4...1,0)V VCREF MAX = VDD - 1,3 V Power down mode LEGEND: (I): Current mode (V): Voltage mode 60/132 ST72141K MOTOR CONTROLLER (Cont'd) The measurement window frequency can be programmed between 195Hz and 25KHz by the means of the SA[3:0] bits in the MPRSR register. In sensorless mode this measurement window can be used to detect either End of Demagnetization or BEMF zero crossing events. Its width can be defined between 5s and 30s in sensorless mode by the OT[1:0] bits in the MPOL register. In sensor mode (SR=1) this off time is fixed at 1.25s. Table 22. Off-Time Table OT1 bit 0 0 1 1 OT0 bit 0 1 0 1 Off-Time Sensorless Mode (SR bit=0) 5 s 10 s 15 s 30 s Off-Time Sensor Mode (SR bit =1) 1.25 s Table 23. Sampling Frequency Selection SA3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SA2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sampling Frequency 25.0 KHz 20.0 KHz 18.1 KHz 15.4 KHz 12.5 KHz 10.0 KHz 6.25 KHz 3.13 KHz 1.56 KHz 1.25 KHz 1.14 KHz 961 Hz 781 Hz 625 Hz 390 Hz 195 Hz Figure 38. Sampling clock generation block MPRSR Register SA[3:0] bits 4 4 MHz1 Frequency logic Off-Time logic 2 OT[1:0] bits MPOL Register (1) The MTC controller input frequency must always be 4 MHz, whatever the crystal frequency is. The appropriate internal frequency can be selected in the Miscellaneous register. R S Toff Q Tsampling 61/132 ST72141K MOTOR CONTROLLER (Cont'd) 8.1.4.4 Channel Manager The channel manager consists of: - A Phase State register with preload and polarity function - A multiplexer to direct the PWM to the odd and/ or even channel group - A tristate buffer asynchronously driven by an emergency input. The block diagram is shown in Figure 39. MPHST Phase State Register A preload register enables software to asynchronously update (during the previous commutation interrupt routine for example) the channel configuration for the next step: the OO[5:0] bits in the MPHST register are copied to the Phase register on a C event. Table 24. Output State OP[5:0] bit 0 0 1 1 OO[5:0] bit 0 1 0 1 MCO[5:0] Pin 1 (OFF) 0-(PWM allowed) 0 (OFF) 1-(PWM allowed) Figure 39. Channel Manager Block Diagram MCRA Register V0C1 bit 16-bit Timer PWM 16-bit timer PWM V Sampling frequency Current comparator output MCRA Register CFF bit MCRA Register DAC bit C MPHST Register OO bits* MPAR Register OE[5:0] bits 6 6 Channel [5:0] Phasen Register* SQ I I V Notes: Reg Regn I V Updated/Shifted on R Updated with Regn+1 on C Current M ode Voltage M ode 2.5-s Filter R events: C Commutation Z BEFM Zero-crossing DS End Of Demagnetization ,H E Em ergency Stop R+/- Ratio Updated (+1 or -1) O Multiplier Overflow 1 Branch taken after C event Branch taken after D event 2 MCRA Register SR bit 3 MCRB Register OS[2:0] bits* MPOL Register OP[5:0] bits MRCA Register MOE bit x6 6 x6 1 MCO4 NMCES MCO1 MCO5 MCO3 * = Preload register, changes taken into account at next C event. 62/132 MCO2 MCO0 ST72141K MOTOR CONTROLLER (Cont'd) Direct access to the phase register is also possible when the DAC bit in the MCRA register is set. Table 25. DAC and MOE Bit Meaning MOE bit 0 1 1 DAC bit x 0 1 Effect on Effect on MTIM Output Timer High Z Clock disabled Standard runStandard running mode ning mode MPHST value same as MPOL Clock disabled value The polarity register is used to match the polarity of the power drivers keeping the same control logic and software. If one of the OPx bits in the MPOL register is set, this means the switch x is ON when MCOx is VDD. Each output status depends also on the momentary state of the PWM, its group (odd or even), and the peripheral state. PWM Features The outputs can be split in two PWM groups in order to differentiate the high side and the low side switches. This output property can be programmed using the OE[5:0] bits in the MPAR register Table 26. Meaning of the OE[5:0] Bits OE[5:0] 0 1 Channel group Even channel Odd channel The OS[2:0] bits in the MCRB register allow the PWM configuration to be configured for each case as shown in Figure 41, Figure 42 and Figure 40. This configuration depends also on the current/ voltage mode (V0C1 bit in the MCRA register) because the OS[2:0] have not the same meaning in voltage mode and in current mode. During demagnetization, the OS2 bit is used to control PWM mode, and it is latched in a preload register so it can be modified when a commutation event occurs. The OS[1:0] bits are used to control the PWM between the D and C events. Warning: In Voltage Mode the OS[2:0] bits have a special configuration value: OS[2:0] = 010. In this mode, there is NO current limitation and NO PWM applied to active outputs. The active outputs are always at 100% whether in demagnetization, or normal mode. Note about demagnetization speed-up: during demagnetization the voltage on the winding has to be as high as possible in order to reduce the demagnetization time. Software can apply a different PWM configuration on the outputs between the C and D events, to force the free wheeling on the appropriate diodes to maximize the demagnetization voltage. Emergency Feature When the NMCES pin goes low - The tristate output buffer is put in HiZ asynchronously - The MOE bit in the MCRA register is reset - An interrupt request is sent to the CPU if the EIM bit in the MIMR register is set This bit can be connected to an alarm signal from the drivers, thermal sensor or any other security component. This feature functions even if the MCU oscillator is off. The multiplexer directs the PWM to the upper channel, the lower channel or both of them alternatively or simultaneously according to the peripheral state. This means that the PWM can affect any of the upper or lower channels allowing the selection of the most appropriate reference potential when freewheeling the motor in order to: - Improve system efficiency - Speed up the demagnetization phase - Enable Back EMF zero crossing detection. 63/132 ST72141K MOTOR CONTROLLER (Cont'd) Figure 40. Step Behaviour of one Output Channel MCO[n] in Voltage Mode (Voltage Mode without polarity effect) OS2 0 1 t] en Ev E[1:0 O 0] [2: O S :0 ] [5 OO de Mo PWM behaviour before D Not Alternate Alternate OS2 OS1 OS0 xxx OS[1:0] 00 01 10 11 PWM behaviour after D On Even Channels On Odd Channels Alternate Odd/Even On all active Channels Step C Demagnetization 1 0 D C Off (0) Voltage (V0C1=0) On (1) X 000 0 Even 1 Odd 001 0 Even 1 Odd 0 Even 010 1 Odd Even 011 0 1 Odd 100 0 1 101 0 1 Even Odd 110 0 1 111 0 1 Even Odd Even Odd Even Odd Even Odd ! WARNING: OS[2:0] = 010 has NO current regulation! 64/132 X ST72141K MOTOR CONTROLLER (Cont'd) Figure 41. Step Behaviour of one Output Channel MCO[n] in Current / Sensorless Mode (Current Mode without polarity effect, sensorless mode: SR=0) OS2 0 1 PWM behaviour before D On Even Channels On Odd Channels OS[1:0] 00 01 10 11 Step C D Demagnetization x 1 0 1 0 1 0 1 0 1 0 OS1 xx 00 11 10 01 C OS0 65/132 C xx 00 11 10 01 1 0 1.25us 01 11 10 00 xx OS1 OS0 1.25us In sensor mode, there is no demagnetisation event and the PWM behaviour is the same for the complete step time. PWM behaviour after D On Even Channels On Odd Channels Alternate Odd/Even On all active Channels Off (0) Current (V0C1=1) X On (1) Even (0) Odd (1) Figure 42. Step Behaviour of one Output Channel MCO[n] in Current / Sensor Mode OS2 (Current Mode without polarity effect, sensor mode: SR=1) OS[1:0] Not used PWM behaviour after D 00 On Even Channels 01 On Odd Channels 10 Alternate Odd/Even 11 On all active Channels Step C Off (0) Current (V0C1=1) Odd (1) On (1) Even (0) X t en ] Ev [1:0 OE 0] [5: OO e d Mo 0 1 Toff 1 0 x Toff 01 11 10 00 xx OS2 t en 0] Ev [5: OE :0] [5 OO de Mo ST72141K MOTOR CONTROLLER (Cont'd) 8.1.5 Low Power Modes Before executing a HALT or WFI instruction, software must stop the motor, and may choose to put the outputs in high impedance. Mode WAIT Description No effect on MTC interface. MTC interrupts exit from Wait mode. MTC registers are frozen. In Halt mode, the MTC interface is inactive. The MTC interface becomes operational again when the MCU is woken up by an interrupt with "exit from Halt mode" capability. 8.1.6 Interrupts Interrupt Event Ratio increment Ratio decrement Multiplier overflow Emergency Stop BEMF Zero-Crossing End of Demagnetization Commutation Enable Exit Exit Event Control from from Flag Bit Wait Halt RPI Yes No RIM RMI Yes No OI OIM Yes No EI EIM Yes No ZI ZIM Yes No DI DIM Yes No CI CIM Yes No HALT The MTC interrupt events are connected to the three interrupt vectors (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction). 66/132 ST72141K MOTOR CONTROLLER (Cont'd) 8.1.7 Register Description TIMER COUNTER REGISTER (MTIM) Read/Write Reset Value: 0000 0000 (00h) 7 T7 T6 T5 T4 T3 T2 T1 0 T0 DEMAGNETIZATION REGISTER (MDREG) Read/Write Reset Value: 0000 0000 (00h) 7 DN7 DN6 DN5 DN4 DN3 DN2 DN1 0 DN0 Bits 7:0 = T[7:0]: MTIM Counter Value. These bits contain the current value of the 8-bit up counter. CAPTURE Z n-1 REGISTER (MZPRV) Read/Write Reset Value: 0000 0000 (00h) 7 ZP7 ZP6 ZP5 ZP4 ZP3 ZP2 ZP1 0 ZP0 Bits 7:0 = DN[7:0]: D Value. These bits contain the compare value for software demagnetization (DN) and the captured value for hardware demagnetization (DH). AN WEIGHT REGISTER (MWGHT) Read/Write Reset Value: 0000 0000 (00h) 7 AN7 AN6 AN5 AN4 AN3 AN2 AN1 0 AN0 Bits 7:0 = ZP[7:0]: Previous Z Value. These bits contain the previous captured BEMF value (ZN-1). CAPTURE Z n REGISTER (MZREG) Read/Write Reset Value: 0000 0000 (00h) 7 ZC7 ZC6 ZC5 ZC4 ZC3 ZC2 ZC1 0 ZC0 Bits 7:0 = AN[7:0]: A Weight Value. These bits contain the AN weight value for the multiplier. In autoswitched mode the MCOMP register is automatically loaded with: Zn x MWGHT 32(d) or ZN-1 x MWGHT 32(d) (*) when a Z event occurs. (*) depending on the DCB bit in the MCRA register. PRESCALER & SAMPLING REGISTER (MPRSR) Read/Write Reset Value: 0000 0000 (00h) 7 SA3 SA2 SA1 SA0 ST3 ST2 ST1 0 ST0 Bits 7:0 = ZC[7:0]: Current Z Value. These bits contain the current captured BEMF value (Z N). COMPARE Cn+1 REGISTER (MCOMP) Read/Write Reset Value: 0000 0000 (00h) 7 DC7 DC6 DC5 DC4 DC3 DC2 DC1 0 DC0 Bits 7:4 = SA[3:0]: Sampling Ratio. These bits contain the sampling ratio value for current mode. Refer to Table 23. Bits 3:0 = ST[3:0]: Step Ratio. These bits contain the step ratio value. It acts as a prescaler for the MTIM timer and is auto incremented/decremented with each R+ or R- event. Refer to Table 20. Bits 7:0 = DC[7:0]: Next Compare Value. These bits contain the compare value for the next commutation (C N+1). 67/132 ST72141K MOTOR CONTROLLER (Cont'd) INTERRUPT MASK REGISTER (MIMR) Read/Write (except bits 7:6) Reset Value: 0000 0000 (00h) 7 HST CL RIM OIM EIM ZIM DIM 0 CIM INTERRUPT STATUS REGISTER (MISR) Read/Write Reset Value: 0000 0000 (00h) 7 0 RPI RMI OI EI ZI DI 0 CI Bit 7 = HST: Hysteresis Comparator Value. This read only bit contains the hysteresis comparator output. 0: Demagnetisation/BEMF comparator is under VREF 1: Demagnetisation/BEMF comparator is above VREF Bit 6 = CL: Current Loop Comparator Value. This read only bit contains the current loop comparator output value. 0: Current detect voltage is under VCREF 1: Current detect voltage is above VCREF Bit 5 = RIM: Ratio update Interrupt Mask bit. 0: Ratio update interrupts (R+ and R-) disabled 1: Ratio update interrupts (R+ and R-) enabled Bit 4 = OIM: Multiplier Overflow Interrupt Mask bit. 0: Multiplier Overflow interrupt disabled 1: Multiplier Overflow interrupt enabled Bit 3 = EIM: Emergency stop Interrupt Mask bit. 0: Emergency stop interrupt disabled 1: Emergency stop interrupt enabled Bit 2 = ZIM: Back EMF Zero-crossing Interrupt Mask bit. 0: BEMF Zero-crossing Interrupt disabled 1: BEMF Zero-crossing Interrupt enabled Bit 1 = DIM: End of Demagnetization Interrupt Mask bit. 0: End of Demagnetization interrupt disabled 1: End of Demagnetization interrupt enabled if the HDM or SDM bit in the MCRB register is set Bit 0 = CIM: Commutation Interrupt Mask bit 0: Commutation Interrupt disabled 1: Commutation Interrupt enabled Bit 7 = Reserved. Forced by hardware to 0. Bit 6 = RPI: Ratio Increment interrupt flag. Autoswitched mode (SWA bit =0): 0: No R+ interrupt pending 1: R+ Interrupt pending Switched mode (SWA bit =1): 0: No R+ action 1: The hardware will increment the ST[3:0] bits when the next commutation occurs and shift all timer registers right. Bit 5 = RMI: Ratio Decrement interrupt flag. Autoswitched mode (SWA bit =0): 0: No R- interrupt pending 1: R- Interrupt pending Switched mode (SWA bit =1): 0: No R- action 1: The hardware will decrement the ST[3:0] bits when the next commutation occurs and shift all timer registers left. Bit 4 = OI: Multiplier Overflow interrupt flag. 0: No Multiplier Overflow interrupt pending 1: Multiplier Overflow interrupt pending Bit 3 = EI: Emergency stop Interrupt flag. 0: No Emergency stop interrupt pending 1: Emergency stop interrupt pending Bit 2 = ZI: BEMF Zero-crossing interrupt flag. 0: No BEMF Zero-crossing Interrupt pending 1: BEMF Zero-crossing Interrupt pending Bit 1 = DI: End of Demagnetization interrupt flag. 0: No End of Demagnetization interrupt pending 1: End of Demagnetization interrupt pending Bit 0 = CI: Commutation interrupt flag 0: No Commutation Interrupt pending 1: Commutation Interrupt pending 68/132 ST72141K MOTOR CONTROLLER (Cont'd) Table 27. Step Ratio Update MOE SWA Clock Read bit bit State 0 x Disabled Enabled Enabled Ratio Ratio Increment Decrement (Slow Down) (Speed-Up) 1 0 1 1 Write the ST[3:0] value directly in the MPRSR register Set RPI bit in Set RMI bit in Always the MISR reg- the MISR regpossi- ister till next ister till next commutation commutation ble Updated automatically according to MZREG value Bit 4 = DAC: Direct Access to phase state register. 0: No Direct Access (reset value). In this mode all the registers with a preload register are taken into account at the C event. 1: Direct Access enabled. In this mode, write a value in the MPHST register to access the outputs directly. All other registers with a preload register are taken into account at the same time. Table 29. DAC Bit Meaning MOE DAC bit bit 0 x 1 0 Effect on Output High Z Standard running mode MPHST register value (depending on MPOL register value) Effect on MTIM Timer Clock disabled Standard running mode Clock disabled CONTROL REGISTER A (MCRA) Read/Write Reset Value: 0000 0000 (00h) 7 MOE RST SR DAC V0C1 SWA CFF 0 DCB 1 1 Bit 7 = MOE: Output Enable bit. 0: Outputs and Clocks disabled 1: Outputs and Clocks enabled MOE bit 0 1 MCO[5:0] Output pin State Tristate Output enabled Note 1: When the MTC clock is disabled, the MTIM counter is not reset but as in this case it is in write access, a reset can be done by software. Note 2: In direct access mode, only logical levels (0 or 1) can be output on the MCOx pins. There is no PWM signal generation in this mode. Bit 3 = V0C1: Voltage/Current Mode 0: Voltage Mode 1: Current Mode Bit 2 = SWA: Switched/Autoswitched Mode 0: Switched Mode 1: Autoswitched Mode Table 30. Switched and Autoswitched Modes SWA bit 0 1 Commutation Type Switched mode Autoswitched mode MCOMP Register access Read/Write Read only Bit 6 = RST: Reset MTC registers. Software can set this bit to reset all MTC registers without resetting the ST7. 0: No MTC register reset 1: Reset all MTC registers Bit 5 = SR: Sensor ON/OFF. 0: Sensorless mode 1: Sensor mode Table 28. Sensor Mode Selection SR bit 0 1 OS2 bit Behaviour of the output enable PWM Sensors not OS2 "Before D" behaviour & "afused enabled ter D" behaviour Sensors OS2 Only "after D" behaviour used disabled Mode Bit 1 = CFF: Current Feedback Filter 0: Current Feedback Filter disabled 1: Current Feedback Filter enabled Bit 0 = DCB: Data Capture bit 0: Use MZPRV (ZN-1) for multiplication 1: Use MZREG (ZN) for multiplication 69/132 ST72141K MOTOR CONTROLLER (Cont'd) Table 31. Multiplier Result DCB bit 0 1 Commutation Delay MCOMP = MWGHT x MZPRV / 32 MCOMP = MWGHT x MZREG / 32 Table 32. Step Behaviour Summary Mode OS PWM after D and OS2 PWM after C [1:0] before C bit and before D bits On even 00 channels On odd Same as 01 channels 0 after D and before C 10 Continuous All active 11 channels On even 00 channels On odd 01 channels 1 Alternate 10 Alternate odd/even All active 11 channels On even 00 channels On odd 01 channels x Unused 10 Alternate odd/even All active 11 channels On even 00 channels On odd 01 On even channels 0 Channels 10 Alternate odd/even All active 11 channels On even 00 channels On odd 01 On odd channels 1 channels 10 Alternate odd/even 11 Sensor (SR=1) 00 x Unused 01 10 11 All active channels On even channels On odd channels Alternate odd/even All active channels 7 VR1 VR0 CPB* HDM* SDM* OS2* OS1 0 OS0 Bits 7:6 = VR[1:0]: BEMF/demagnetization Reference threshold These bits select the VREF value as shown in the following table. VR1 0 0 1 1 VR0 0 1 0 1 VREF Voltage threshold 0.2V 0.6V 1.2V 2.5V Voltage mode(V0C1=0) Current mode (V0C1=1) Bit 4 = HDM*: Hardware Demagnetization event Mask bit 0: Hardware Demagnetization disabled 1: Hardware Demagnetization enabled Bit 3 = SDM*: Software Demagnetization event Mask bit 0: Software Demagnetization disabled 1: Software Demagnetization enabled Bits 2:0 = OS2*,OS[1:0]: Operating output mode Selection bits Refer to the Step behaviour diagrams (Figure 40, Figure 41, Figure 42) and Table 32. These bits are used to configure the various PWM output configurations. Note: The OS2 bit is the only one with a preload register. Note: For more details, see Step behaviour diagrams (Figure 40, Figure 41, and Figure 42). * Preload bits, new value taken into account at next C event. 70/132 Sensorless (SR=0) Bit 5 = CPB*: Compare Bit for Zero-crossing detection. 0: Zero crossing detection on falling edge 1: Zero crossing detection on rising edge Sensor (SR=1) Sensorless (SR=0) CONTROL REGISTER B (MCRB) Read/Write Reset Value: 0000 0000 (00h) ST72141K MOTOR CONTROLLER (Cont'd) PHASE STATE REGISTER (MPHST) Read/Write Reset Value: 0000 0000 (00h) 7 IS1* IS0* OO5* OO4* OO3* OO2* OO1* 0 OO0* 1: Zero-crossing and End of Demagnetisation have same edge Bit 6 = REO: Read on Even or Odd channel bit 0: Read the BEMF signal during the off time on even channels 1: Read on odd channels Bits 5:0 = OE[5:0]: Output Parity Mode. 0: Output channel is Even 1: Output channel Odd POLARITY REGISTER (MPOL) Read/Write Reset Value: 0000 0000 (00h) 7 OT1 OT0 OP5 OP4 OP3 OP2 OP1 0 OP0 Bits 7:6 = IS[1:0]*: Input Selection bits These bits select the input to connect to comparator as shown in the following table: Table 33. Input Channel Selection IS1 0 0 1 1 IS0 0 1 0 1 Channel selected MCIA MCIB MCIC Not Used Bits 5:0 =OO[5:0]*: Channel On/Off bits These bits are used to switch channels on/off at the next C event if the DAC bit =0 or directly if DAC=1 0: Channel Off, the relevant switch is OFF, no PWM possible 1: Channel On the relevant switch is ON, PWM is possible. Table 34. OO[5:0] Bit Meaning OO[5:0] 0 1 Output Channel State Inactive Active Bits 7:6 = OT[1:0]: Off Time selection. These bits are used to select the off time in sensorless mode as shown in the following table. Table 35. Off-Time bit Meaning Off-Time OT1 0 0 1 1 OT0 0 1 0 1 Sensorless Mode (SR=0) 5 s 10 s 15 s 30 s Off-Time Sensor Mode (SR=1) 1.25 s * Preload bits, new value taken into account at next C event. PARITY REGISTER (MPAR) Read/Write Reset Value: 0000 0000 (00h) 7 ZVD REO OE5 OE4 OE3 OE2 OE1 0 OE0 Bits 5:0 = OP[5:0]: Output channel polarity. These bits are used together with the OO[5:0] bits in the MPHST register to control the output channels. 0: Output channel is Active Low 1: Output channel is Active High. Table 36. Output Channel State Control OP[5:0] bit 0 0 1 1 OO[5:0] bit 0 1 0 1 MCO[5:0] pin 1 (Off) 0 (PWM possible) 0 (Off) 1 (PWM possible) Bit 7 = ZVD: Z vs D edge polarity. 0: Zero-crossing and End of Demagnetisation have opposite edges 71/132 ST72141K MOTOR CONTROLLER (Cont'd) Note: The CPB, HDM, SDM, OS2 bits in the MCRB and the bits OE[5:0] are marked with *. It means that these bits are taken into account at the following commutation event (in normal mode) or when a value is written in the MPHST register when in direct access mode. For more details, refer to the description of the DAC bit in the MCRA register. The use of a Preload register allows all the registers to be updated at the same time. Warning: Access to Preload registers Special care has to be taken with Preload registers, especially when using the ST7 BSET and BRES instructions on MTC registers. For instance, while writing to the MPHST register, you will write the value in the preload register. However, while reading at the same address, you will get the current value in the register and not the value of the preload register. All preload registers are loaded in the real registers at the same time. In normal mode this is done automatically when a C event occurs, however in direct access mode (DAC bit=1) the preload registers are loaded as soon as a value is written in the MPHST register. 72/132 Microcontroller REO bit DS,H C M CIC M CIA 2 ZVD bit CPBn bit ISn bit Board + Motor 20s / D Z QD 1 or or or or 20s / C CP C DS,H VR1-0 CPBn bit 1 2 + MCIB VREF SR bit DH HDMn bit MR R C A eg. VD D (I) OCP1A 1 / 32 Cext 16-bit Timer A used as PWM 4M Hz 1/5 V0C1 bit R xt 1e V I R+ (I) (V) VCREF MOTOR CONTROLLER (Cont'd) Figure 43. Detailed view of the MTC +1 1 A 1/128 SR bit HV 3 SWA bit Z MCO0 V I M CO2 clr 0 1 M TIM = FFh? R xt 2e 1/ 2 (V ) ST3-0 bits 4 1 / 2Ratio -1 OSn bits M ZREG < 55h? RC ck SA3-0 & OT1-0 bits MTIM [8-bit Up Counter] 8 MCO4 DH x6 x6 Z MDREG Reg [Dn] SQ Com pare R SDM bit n MZREG Reg [Zn] B Z MPHSTn Reg A M CO3 M CO5 M CO1 C MZPRV Reg [Zn-1] DCB bit n-1 n Notes: Reg Regn 6 1 I V NMCES Updated/Shifted on R Updated with Regn+1 on C Current M ode Voltage M ode MW GHT Reg [an+1] DS 6 DS,H 8 8 O A x B / 32 O R-/+ SW bit A MIMR Reg Compare DS,H C M ISR Reg Z CFF bit E M POL Reg MCOM Reg [Cn+1] P M PAR Reg MOE bit 8 3 set 20s / C M CCFI C 2.5-s / PW M + - VCREF A events: C Commutation Z BEFM Zero-crossing DS End Of Demagnetization ,H E Em ergency Stop +/- Ratio Updated (+1 or -1) R O Multiplier Overflow 1 Branch taken after C event 2 ST72141K 73/132 Branch taken after D event ST72141K MOTOR CONTROLLER (Cont'd) Table 37. MTC Register Map and Reset Values Address (Hex.) 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh Register Name MTIM Reset Value MZPRV Reset Value MZREG Reset Value MCOMP Reset Value MDREG Reset Value MWGHT Reset Value MPRSR Reset Value MIMR Reset Value MISR Reset Value MCRA Reset Value MCRB Reset Value MPHST Reset Value MPAR Reset Value MPOL Reset Value 7 T7 0 ZP7 0 ZC7 0 DC7 0 DN7 0 AN7 0 SA3 0 HST 0 0 MOE 0 VR1 0 IS1 0 ZVD 0 OT1 0 6 T6 0 ZP6 0 ZC6 0 DC6 0 DN6 0 AN6 0 SA2 0 CL 0 RPI 0 RST 0 VR0 0 IS0 0 REO 0 OT0 0 5 T5 0 ZP5 0 ZC5 0 DC5 0 DN5 0 AN5 0 SA1 0 RIM 0 RMI 0 SR 0 CPB 0 OO5 0 OE5 0 OP5 0 4 T4 0 ZP4 0 ZC4 0 DC4 0 DN4 0 AN4 0 SA0 0 OIM 0 OI 0 DAC 0 HDM 0 OO4 0 OE4 0 OP4 0 3 T3 0 ZP3 0 ZC3 0 DC3 0 DN3 0 AN3 0 ST3 0 EIM 0 EI 0 V0C1 0 SDM 0 OO3 0 OE3 0 OP3 0 2 T2 0 ZP2 0 ZC2 0 DC2 0 DN2 0 AN2 0 ST2 0 ZIM 0 ZI 0 SWA 0 OS2 0 OO2 0 OE2 0 OP2 0 1 T1 0 ZP1 0 ZC1 0 DC1 0 DN1 0 AN1 0 ST1 0 DIM 0 DI 0 CFF 0 OS1 0 OO1 0 OE1 0 OP1 0 0 T0 0 ZP0 0 ZC0 0 DC0 0 DN0 0 AN0 0 ST0 0 CIM 0 CI 0 DCB 0 OS0 0 OO0 OE0 0 OP0 0 74/132 ST72141K 8.2 WATCHDOG TIMER (WDG) 8.2.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. Figure 44. Watchdog Block Diagram 8.2.2 Main Features s Programmable timer (64 increments of 12288 CPU cycles) s Programmable reset s Reset (if watchdog activated) after a HALT instruction or when the T6 bit reaches zero s Watchdog Reset indicated by status flag RESET WATCHDOG CONTROL REGISTER (CR) WDGA T6 T5 T4 T3 T2 T1 T0 7-BIT DOWNCOUNTER fCPU CLOCK DIVIDER / 12288 75/132 ST72141K WATCHDOG TIMER (Cont'd) 8.2.3 Functional Description The counter value stored in the CR register (bits T6:T0), is decremented every 12288 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 become cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 38 . Watchdog Timing (fCPU = 8 MHz)): - The WDGA bit is set (watchdog enabled) - The T6 bit is set to prevent generating an immediate reset - The T5:T0 bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 38. Watchdog Timing (fCPU = 8 MHz) CR Register initial value FFh C0h WDG timeout period (ms) 98.304 1.536 8.2.6 Register Description CONTROL REGISTER (CR) Read /Write Reset Value: 0111 1111 (7Fh) 7 WDGA T6 T5 T4 T3 T2 T1 0 T0 Bit 7= WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared) if WDGA=1. STATUS REGISTER (SR) Read /Write Reset Value*: xxxx xxxx0 7 0 WDOGF Max Min Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset. 8.2.4 Low Power Modes Mode WAIT HALT Description No effect on Watchdog. Immediate reset generation as soon as the HALT instruction is executed if the Watchdog is activated (WDGA bit is set). Bit 0 = WDOGF Watchdog flag. This bit is set by a watchdog reset and cleared by software or a power on/off reset. This bit is useful for distinguishing power/on off or external reset and watchdog reset. 0: No Watchdog reset occurred 1: Watchdog reset occurred * Only by software and power on/off reset 8.2.5 Interrupts None. 76/132 ST72141K WATCHDOG TIMER (Cond't) Table 39. Watchdog Timer Register Map and Reset Values Address (Hex.) 0024h 0025h Register Label WDGCR Reset Value WDGSR Reset Value 7 WDGA 0 0 6 T6 1 0 5 T5 1 0 4 T4 1 0 3 T3 1 0 2 T2 1 0 1 T1 1 0 0 T0 1 WDOGF 0 77/132 ST72141K 8.3 16-BIT TIMER 8.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (input capture) or generating up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B). 8.3.2 Main Features s Programmable prescaler: fCPU divided by 2, 4 or 8. s Overflow status flag and maskable interrupt s External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge s Output compare functions with: - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Input capture functions with: - 2 dedicated 16-bit registers - 2 dedicated active edge selection signals - 2 dedicated status flags - 1 dedicated maskable interrupt s Pulse Width Modulation mode (PWM) s One Pulse mode s 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 45. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be `1'. 8.3.3 Functional Description 8.3.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): - Counter High Register (CHR) is the most significant byte (MS Byte). - Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) - Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). - Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR). (See note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 40 Clock Control Bits. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency. 78/132 ST72141K 16-BIT TIMER (Cont'd) Figure 45. Timer Block Diagram ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE 8 high 8 low 8-bit buffer 8 high low 8 high 8 low 8 high 8 low 8 high 8 low 8 EXEDG 16 1/2 1/4 1/8 EXTCLK pin COUNTER REGISTER ALTERNATE COUNTER REGISTER OUTPUT COMPARE REGISTER 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 INPUT CAPTURE REGISTER 2 16 16 16 CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT OUTPUT COMPARE CIRCUIT EDGE DETECT CIRCUIT1 ICAP1 pin 6 EDGE DETECT CIRCUIT2 ICAP2 pin LATCH1 ICF1 OCF1 TOF ICF2 OCF2 0 OCMP1 pin OCMP2 pin 0 0 LATCH2 (Status Register) SR ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG (Control Register 1) CR1 (Control Register 2) CR2 (See note) TIMER INTERRUPT Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table) 79/132 ST72141K 16-BIT TIMER (Cont'd) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence At t0 Read MS Byte Other instructions Read At t0 +t LS Byte Returns the buffered LS Byte is buffered LS Byte value at t0 Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: - The TOF bit of the SR register is set. - A timer interrupt is generated if: - TOIE bit of the CR1 register is set and - I bit of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset). 8.3.3.2 External Clock The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. 80/132 ST72141K 16-BIT TIMER (Cont'd) Figure 46. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003 Figure 47. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001 Figure 48. Counter Timing Diagram, internal clock divided by 8 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000 TIMER OVERFLOW FLAG (TOF) Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running. 81/132 ST72141K 16-BIT TIMER (Cont'd) 8.3.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected by the ICAPi pin (see figure 5). ICiR MS Byte ICiHR LS Byte ICiLR The ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the input capture function, select the following in the CR2 register: - Select the timer clock (CC[1:0]) (see Table 40 Clock Control Bits). - Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). And select the following in the CR1 register: - Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). When an input capture occurs: - The ICFi bit is set. - The ICiR register contains the value of the free running counter on the active transition on the ICAPi pin (see Figure 50). - A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, the transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One Pulse mode and PWM mode only the input capture 2 function can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh). 82/132 ST72141K 16-BIT TIMER (Cont'd) Figure 49. Input Capture Block Diagram ICAP1 pin ICAP2 pin EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1 ICIE (Control Register 1) CR1 IEDG1 (Status Register) SR IC2R Register IC1R Register ICF1 ICF2 0 0 0 16-BIT (Control Register 2) CR2 CC1 CC0 IEDG2 16-BIT FREE RUNNING COUNTER Figure 50. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: Active edge is rising edge. FF03 FF01 FF02 FF03 83/132 ST72141K 16-BIT TIMER (Cont'd) 8.3.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCiE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. OCiR MS Byte OCiHR LS Byte OCiLR - The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). - A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR = Where: t * fCPU PRESC t fCPU = Output compare period (in seconds) = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 40 Clock Control Bits) These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: - Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. - Select the timer clock (CC[1:0]) (see Table 40 Clock Control Bits). And select the following in the CR1 register: - Select the OLVLi bit to applied to the OCMPi pins after the match occurs. - Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: - OCFi bit is set. If the timer clock is an external clock, the formula is: OCiR = t * fEXT Where: t fEXT = Output compare period (in seconds) = External timer clock frequency (in hertz) Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: - Write to the OCiHR register (further compares are inhibited). - Read the SR register (first step of the clearance of the OCFi bit, which may be already set). - Write to the OCiLR register (enables the output compare function and clears the OCFi bit). 84/132 ST72141K 16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 52). This behaviour is the same in OPM or PWM mode. When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 53). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. Figure 51. Output Compare Block Diagram Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated. FOLVLi bits have no effect in either One-Pulse mode or PWM mode. 16 BIT FREE RUNNING COUNTER OC1E OC2E CC1 CC0 16-bit OUTPUT COMPARE CIRCUIT (Control Register 2) CR2 (Control Register 1) CR1 OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch 1 OCMP1 Pin OCMP2 Pin 16-bit 16-bit OC1R Register OCF1 OCF2 0 0 0 Latch 2 OC2R Register (Status Register) SR 85/132 ST72141K 16-BIT TIMER (Cont'd) Figure 52. Output Compare Timing Diagram, fTIMER =fCPU/2 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3 Figure 53. Output Compare Timing Diagram, fTIMER =fCPU/4 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3 86/132 ST72141K 16-BIT TIMER (Cont'd) 8.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse. - Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: - Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. - Set the OPM bit. - Select the timer clock CC[1:0] (see Table 40 Clock Control Bits). Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: OCiR Value = t * fCPU PRESC -5 Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 40 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 54). Notes: 1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedicated to One Pulse mode. One Pulse mode cycle When event occurs on ICAP1 OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set When Counter = OC1R OCMP1 = OLVL1 Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. 87/132 ST72141K 16-BIT TIMER (Cont'd) Figure 54. One Pulse Mode Timing Example COUNTER ICAP1 OCMP1 FFFC FFFD FFFE 2ED0 2ED1 2ED2 2ED3 FFFC FFFD OLVL2 OLVL1 OLVL2 compare1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 55. Pulse Width Modulation Mode Timing Example COUNTER 34E2 FFFC FFFD FFFE OCMP1 2ED0 2ED1 2ED2 34E2 FFFC OLVL2 OLVL1 OLVL2 compare2 compare1 compare2 Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1 88/132 ST72141K 16-BIT TIMER (Cont'd) 8.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated. Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if OLVL1=0 and OLVL2=1, using the formula in the opposite column. 3. Select the following in the CR1 register: - Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC1R register. - Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: - Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function. - Set the PWM bit. - Select the timer clock (CC[1:0]) (see Table 40 Clock Control Bits). If OLVL1=1 and OLVL2=0, the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. The OCiR register value required for a specific timing application can be calculated using the following formula: OCiR Value = t * fCPU PRESC -5 Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 40 Clock Control Bits) If the timer clock is an external clock the formula is: OCiR = t * fEXT -5 Where: t = Signal or pulse period (in seconds) fEXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 55) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also generate an interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. Pulse Width Modulation cycle When Counter = OC1R OCMP1 = OLVL1 When Counter = OC2R OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set 89/132 ST72141K 16-BIT TIMER (Cont'd) 8.3.4 Low Power Modes Mode WAIT Description No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with "exit from HALT mode" capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register. HALT 8.3.5 Interrupts Interrupt Event Input Capture 1 event/Counter reset in PWM mode Input Capture 2 event Output Compare 1 event (not available in PWM mode) Output Compare 2 event (not available in PWM mode) Timer Overflow event Event Flag ICF1 ICF2 OCF1 OCF2 TOF Enable Control Bit ICIE OCIE TOIE Exit from Wait Yes Yes Yes Yes Yes Exit from Halt No No No No No Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 8.3.6 Summary of Timer modes MODES Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse mode PWM Mode 1) 2) Input Capture 1 Yes Yes No No AVAILABLE RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes Yes Yes 1) No Partially 2) Not Recommended 3) Not Recommended No No See note 4 in Section 8.3.3.5 One Pulse Mode See note 5 in Section 8.3.3.5 One Pulse Mode 3) See note 4 in Section 8.3.3.6 Pulse Width Modulation Mode 90/132 ST72141K 16-BIT TIMER (Cont'd) 8.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h) 7 0 Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. 91/132 ST72141K 16-BIT TIMER (Cont'd) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 0 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bits 3:2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 40. Clock Control Bits Timer Clock fCPU / 4 fCPU / 2 fCPU / 8 External Clock (where available) CC1 0 0 1 1 CC0 0 1 0 1 Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the internal Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the internal Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. Bit 5 = OPM One Pulse mode. 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register. Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin (EXTCLK) will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register. 92/132 ST72141K 16-BIT TIMER (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 0 0 0 0 INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). 7 MSB 0 LSB Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter has rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2-0 = Reserved, forced by hardware to 0. INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). 7 MSB 0 LSB OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB 0 LSB OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. 7 MSB 0 LSB 93/132 ST72141K 16-BIT TIMER (Cont'd) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB 0 LSB ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. 7 MSB 0 LSB OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. 7 MSB 0 LSB ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register. 7 0 LSB COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. 7 MSB 0 LSB MSB INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event). 7 0 LSB COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit. 7 MSB 0 LSB MSB INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event). 7 MSB 0 LSB 94/132 ST72141K 16-BIT TIMER (Cont'd) Table 41. 16-Bit Timer Register Map and Reset Values Address (Hex.) Register Label 7 ICIE 0 OC1E 0 ICF1 0 MSB MSB MSB MSB MSB MSB MSB 1 MSB 1 MSB 1 MSB 1 MSB MSB 6 OCIE 0 OC2E 0 OCF1 0 5 TOIE 0 OPM 0 TOF 0 4 FOLV2 0 PWM 0 ICF2 0 3 FOLV1 0 CC1 0 OCF2 0 2 OLVL2 0 CC0 0 0 1 IEDG1 0 IEDG2 0 0 0 OLVL1 0 EXEDG 0 0 LSB LSB LSB LSB LSB LSB LSB 1 LSB 0 LSB 1 LSB 0 LSB LSB - Timer A: 32 CR1 Timer B: 42 Reset Value Timer A: 31 CR2 Timer B: 41 Reset Value Timer A: 33 SR Timer B: 43 Reset Value Timer A: 34 ICHR1 Timer B: 44 Reset Value Timer A: 35 ICLR1 Timer B: 45 Reset Value Timer A: 36 OCHR1 Timer B: 46 Reset Value Timer A: 37 OCLR1 Timer B: 47 Reset Value Timer A: 3E OCHR2 Timer B: 4E Reset Value Timer A: 3F OCLR2 Timer B: 4F Reset Value Timer A: 38 CHR Timer B: 48 Reset Value Timer A: 39 CLR Timer B: 49 Reset Value Timer A: 3A ACHR Timer B: 4A Reset Value Timer A: 3B ACLR Timer B: 4B Reset Value Timer A: 3C ICHR2 Timer B: 4C Reset Value Timer A: 3D ICLR2 Timer B: 4D Reset Value - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 - 1 - 1 - 1 - 1 - 0 - - - - - - - 95/132 ST72141K 8.4 SERIAL PERIPHERAL INTERFACE (SPI) 8.4.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. The SPI is normally used for communication between the microcontroller and external peripherals or another microcontroller. Refer to the Pin Description chapter for the devicespecific pin-out. 8.4.2 Main Features s Full duplex, three-wire synchronous transfers s Master or slave operation s Four master mode frequencies s Maximum slave mode frequency = fCPU/4. s Four programmable master bit rates s Programmable clock polarity and phase s End of transfer interrupt flag s Write collision flag protection s Master mode fault protection capability. 8.4.3 General description The SPI is connected to external devices through 4 alternate pins: - MISO: Master In Slave Out pin - MOSI: Master Out Slave In pin - SCK: Serial Clock pin - SS: Slave select pin A basic example of interconnections between a single master and a single slave is illustrated on Figure 56. The MOSI pins are connected together as are MISO pins. In this way data is transferred serially between master and slave (most significant bit first). When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. A status flag is used to indicate that the I/O operation is complete. Four possible data/clock timing relationships may be chosen (see Figure 59) but master and slave must be programmed with the same timing mode. Figure 56. Serial Peripheral Interface Master/Slave MASTER MSBit LSBit MISO MISO MSBit SLAVE LSBit 8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER MOSI MOSI SPI CLOCK GENERATOR SCK SCK +5V SS SS 96/132 ST72141K SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 57. Serial Peripheral Interface Block Diagram Internal Bus Read Read Buffer DR IT request MOSI MISO 8-Bit Shift Register SPIF WCOL - MODF - SR - Write SPI STATE CONTROL SCK SS CR SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 MASTER CONTROL SERIAL CLOCK GENERATOR 97/132 ST72141K SERIAL PERIPHERAL INTERFACE (Cont'd) 8.4.4 Functional Description Figure 56 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: - A Control Register (CR) - A Status Register (SR) - A Data Register (DR) Refer to the CR, SR and DR registers in Section 8.4.7for the bit definitions. 8.4.4.1 Master Configuration In a master configuration, the serial clock is generated on the SCK pin. Procedure - Select the SPR0 & SPR1 bits to define the serial clock baud rate (see CR register). - Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 59). - The SS pin must be connected to a high level signal during the complete byte transmit sequence. - The MSTR and SPE bits must be set (they remain set only if the SS pin is connected to a high level signal). In this configuration the MOSI pin is a data output and to the MISO pin is a data input. Transmit sequence The transmit sequence begins when a byte is written the DR register. The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set 2. A read to the DR register. Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. 98/132 ST72141K SERIAL PERIPHERAL INTERFACE (Cont'd) 8.4.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure - For correct data transfer, the slave device must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure 59. - The SS pin must be connected to a low level signal during the complete byte transmit sequence. - Clear the MSTR bit and set the SPE bit to assign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt is generated if SPIE bit is set and I bit in CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set. 2.A read to the DR register. Notes: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 8.4.4.6). Depending on the CPHA bit, the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision (see Section 8.4.4.4). 99/132 ST72141K SERIAL PERIPHERAL INTERFACE (Cont'd) 8.4.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of eight clock pulses. The SS pin allows individual selection of a slave device; the other slave devices that are not selected do not interfere with the SPI transfer. Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred. This bit affects both master and slave modes. The combination between the CPOL and CPHA (clock phase) bits selects the data capture clock edge. Figure 59, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. The SS pin is the slave device select input and can be driven by the master device. The master device applies data to its MOSI pinclock edge before the capture clock edge. CPHA bit is set The second edge on the SCK pin (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on the occurrence of the second clock transition. No write collision should occur even if the SS pin stays low during a transfer of several bytes (see Figure 58). CPHA bit is reset The first edge on the SCK pin (falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the MSBit capture strobe. Data is latched on the occurrence of the first clock transition. The SS pin must be toggled high and low between each byte transmitted (see Figure 58). To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow it to be altered. Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision. Figure 58. CPHA / SS Timing Diagram MOSI/MISO Master SS Slave SS (CPHA=0) Slave SS (CPHA=1) Byte 1 Byte 2 Byte 3 VR02131A 100/132 ST72141K SERIAL PERIPHERAL INTERFACE (Cont'd) Figure 59. Data Clock Timing Diagram CPHA =1 SCLK (with CPOL = 1) SCLK (with CPOL = 0) MISO (from master) MOSI (from slave) SS (to slave) CAPTURE STROBE MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit CPHA =0 CPOL = 1 CPOL = 0 MISO (from master) MOSI (from slave) SS (to slave) CAPTURE STROBE MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter. VR02131B 101/132 ST72141K SERIAL PERIPHERAL INTERFACE (Cont'd) 8.4.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation. In Slave mode When the CPHA bit is set: The slave device will receive a clock (SCK) edge prior to the latch of the first data transfer. This first clock edge will freeze the data in the slave device DR register and output the MSBit on to the external MISO pin of the slave device. The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge. When the CPHA bit is reset: Data is latched on the occurrence of the first clock transition. The slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the DR register after its SS pin has been pulled low. For this reason, the SS pin must be high, between each data byte transfer, to allow the CPU to write in the DR register without generating a write collision. In Master mode Collision in the master device is defined as a write of the DR register while the internal serial clock (SCK) is in the process of transfer. The SS pin signal must be always high on the master device. WCOL bit The WCOL bit in the SR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 60). Figure 60. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SR OR THEN Read SR THEN 2nd Step Read DR SPIF =0 WCOL=0 Write DR SPIF =0 WCOL=0 if no transfer has started WCOL=1 if a transfer has started before the 2nd step Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step Read SR THEN 2nd Step Read DR WCOL=0 Note: Writing to the DR register instead of reading in it does not reset the WCOL bit 102/132 ST72141K SERIAL PERIPHERAL INTERFACE (Cont'd) 8.4.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: - The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read or write access to the SR register while the MODF bit is set. 2. A write to the CR register. Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing sequence of the MODF bit. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state using an interrupt routine. 8.4.4.6 Overrun Condition An overrun condition occurs when the master device has sent several data bytes and the slave device has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripheral. 103/132 ST72141K SERIAL PERIPHERAL INTERFACE (Cont'd) 8.4.4.7 Single Master and Multimaster Configurations For more security, the slave device may respond There are two types of SPI systems: to the master with the received data byte. Then the - Single Master System master will receive the previous byte back from the - Multimaster System slave device if all MISO and MOSI pins are connected and the slave has not written its DR register. Single Master System Other transmission security methods can use A typical single master system may be configured, ports for handshake lines or data bytes with comusing an MCU as the master and four MCUs as mand fields. slaves (see Figure 61). Multi-master System The master device selects the individual slave deA multi-master system may also be configured by vices by using four pins of a parallel port to control the user. Transfer of master control could be imthe four SS pins of the slave devices. plemented using a handshake method through the The SS pins are pulled high during reset since the I/O ports or by an exchange of code messages master device ports will be forced to be inputs at through the serial peripheral interface system. that time, thus disabling the slave devices. The multi-master system is principally handled by the MSTR bit in the CR register and the MODF bit Note: To prevent a bus conflict on the MISO line in the SR register. the master allows only one active slave device during a transmission. Figure 61. Single Master Configuration SS SCK Slave MCU MOSI MISO SCK Slave MCU SS SCK Slave MCU SS SCK Slave MCU SS MOSI MISO MOSI MISO MOSI MISO MOSI MISO SCK Master MCU 5V SS Ports 104/132 ST72141K SERIAL PERIPHERAL INTERFACE (Cont'd) 8.4.5 Low Power Modes Mode WAIT HALT Description No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability. 8.4.6 Interrupts Interrupt Event SPI End of Transfer Event Master Mode Fault Event Event Flag SPIF MODF Enable Control Bit SPIE Exit from Wait Yes Yes Exit from Halt No No Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 105/132 ST72141K SERIAL PERIPHERAL INTERFACE (Cont'd) 8.4.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 0 SPR0 Bit 3 = CPOL Clock polarity. This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. Bit 2 = CPHA Clock phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Bit 1:0 = SPR[1:0] Serial peripheral rate. These bits are set and cleared by software.Used with the SPR2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. These 2 bits have no effect in slave mode. Table 42. Serial Peripheral Baud Rate Serial Clock fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 fCPU/128 SPR2 1 0 0 1 0 0 SPR1 0 0 0 1 1 1 SPR0 0 0 1 0 0 1 Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1 or MODF=1 in the SR register Bit 6 = SPE Serial peripheral output enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 8.4.4.5 Master Mode Fault). 0: I/O port connected to pins 1: SPI alternate functions connected to pins The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. Bit 5 = SPR2 Divider Enable. this bit is set and cleared by software and it is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 42. 0: Divider by 2 enabled 1: Divider by 2 disabled Bit 4 = MSTR Master. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 8.4.4.5 Master Mode Fault). 0: Slave mode is selected 1: Master mode is selected, the function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed. 106/132 ST72141K SERIAL PERIPHERAL INTERFACE (Cont'd) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) 7 SPIF WCOL MODF 0 - DATA I/O REGISTER (DR) Read/Write Reset Value: Undefined 7 D7 D6 D5 D4 D3 D2 D1 0 D0 Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register). 0: Data transfer is in progress or has been approved by a clearing sequence. 1: Data transfer between the device and an external device has been completed. Note: While the SPIF bit is set, all writes to the DR register are inhibited. Bit 6 = WCOL Write Collision status. This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 60). 0: No write collision occurred 1: A write collision has been detected Bit 5 = Unused. Bit 4 = MODF Mode Fault flag. This bit is set by hardware when the SS pin is pulled low in master mode (see Section 8.4.4.5 Master Mode Fault). An SPI interrupt can be generated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bits 3-0 = Unused. The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. Warning: A write to the DR register places data directly into the shift register for transmission. A read to the the DR register returns the value located in the buffer and not the contents of the shift register (See Figure 57 ). 107/132 ST72141K SERIAL PERIPHERAL INTERFACE (Cont'd) Table 43. SPI Register Map and Reset Values Address (Hex.) 0021h 0022h 0023h Register Label SPIDR Reset Value SPICR Reset Value SPISR Reset Value 7 MSB x SPIE 0 SPIF 0 6 5 4 3 2 1 0 LSB x SPR0 x 0 x SPE 0 WCOL 0 x SPR2 0 0 x MSTR 0 MODF 0 x CPOL x 0 x CPHA x 0 x SPR1 x 0 108/132 ST72141K 8.5 8-BIT A/D CONVERTER (ADC) 8.5.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 8 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 8 different sources. The result of the conversion is stored in a 8-bit Data Register. The A/D converter is controlled through a Control/Status Register. 8.5.2 Main Features s 8-bit conversion s Up to 8 channels with multiplexed input s Linear successive approximation s Data register (DR) which contains the results s Conversion complete status flag s On/Off bit (to reduce consumption) The block diagram is shown in Figure 62. Figure 62. ADC Block Diagram COCO - ADON 0 - CH2 CH1 CH0 (Control Status Register) CSR AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 ANALOG MUX SAMPLE & HOLD ANALOG TO DIGITAL CONVERTER fCPU AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 (Data Register) DR 109/132 ST72141K 8-BIT A/D CONVERTER (ADC) (Cont'd) 8.5.3 Functional Description The high level reference voltage VDDA must be connected externally to the V DD pin. The low level reference voltage V SSA must be connected externally to the VSS pin. In some devices (refer to device pin out description) high and low level reference voltages are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be degraded by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. Figure 63. Recommended Ext. Connections VDD 0.1F VDDA VSSA ST7 RAIN VAIN Px.x/AINx Characteristics: The conversion is monotonic, meaning the result never decreases if the analog input does not and never increases if the analog input does not. If input voltage is greater than or equal to VDD (voltage reference high) then results = FFh (full scale) without overflow indication. If input voltage VSS (voltage reference low) then the results = 00h. The conversion time is 64 CPU clock cycles including a sampling time of 31.5 CPU clock cycles. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. The A/D converter is linear and the digital result of the conversion is given by the formula: Digital result = 255 x Input Voltage Reference Voltage The accuracy of the conversion is described in the Electrical Characteristics Section. Procedure: Refer to the CSR and DR register description section for the bit definitions. Each analog input pin must be configured as input, no pull-up, no interrupt. Refer to the "I/O Ports" chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the CSR register: - Select the CH2 to CH0 bits to assign the analog channel to convert. Refer to Table 44 Channel Selection. - Set the ADON bit. Then the A/D converter is enabled after a stabilization time (typically 30 s). It then performs a continuous conversion of the selected channel. When a conversion is complete - The COCO bit is set by hardware. - No interrupt is generated. - The result is in the DR register. A write to the CSR register aborts the current conversion, resets the COCO bit and starts a new conversion. 8.5.4 Low Power Modes Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed. Mode WAIT Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilisation time before accurate conversions can be performed. HALT 8.5.5 Interrupts None. Where Reference Voltage is VDD - VSS. 110/132 ST72141K 8-BIT A/D CONVERTER (ADC) (Cont'd) 8.5.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) 7 COCO ADON 0 CH2 CH1 0 CH0 These bits are set and cleared by software. They select the analog input to convert. Table 44. Channel Selection Pin* AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 CH2 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 Bit 7 = COCO Conversion Complete This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete. 1: Conversion can be read from the DR register. Bit 6 = Reserved. Must always be cleared. Bit 5 = ADON A/D converter On This bit is set and cleared by software. 0: A/D converter is switched off. 1: A/D converter is switched on. Note: A typical 30 s delay time is necessary for the ADC to stabilize when the ADON bit is set. Bit 4 = Reserved. Forced by hardware to 0. Bit 3 = Reserved. Must always be cleared. Bits 2:0: CH[2:0] Channel Selection *IMPORTANT NOTE: The number of pins AND the channel selection vary according to the device. REFER TO THE DEVICE PINOUT). DATA REGISTER (DR) Read Only Reset Value: 0000 0000 (00h) 7 AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 AD0 Bit 7:0 = AD[7:0] Analog Converted Value This register contains the converted analog value in the range 00h to FFh. Reading this register resets the COCO flag. Table 45. ADC Register Map and Reset Values Address (Hex.) 0070h Register Label ADCDR Reset Value ADCCSR Standard Reset Value 7 IS11 0 COCO 0 6 IS10 0 5 MCO 0 ADON 0 4 IS21 0 3 IS20 0 2 CP1 0 CH2 0 1 CP0 0 CH1 0 0 SMS 0 CH0 0 0071h 0 0 0 111/132 ST72141K 9 INSTRUCTION SET 9.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5 The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do Table 46. ST7 Addressing Mode Overview Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip Syntax so, most of the addressing modes may be subdivided in two sub-modes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes. Destination/ Source Pointer Address (Hex.) Pointer Size (Hex.) +0 +1 Length (Bytes) 00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC-128/PC+127 00..FF 00..FF 00..FF 00..FF byte 00..FF byte 1) +1 +2 + 0 (with X register) + 1 (with Y register) +1 +2 00..FF 00..FF 00..FF 00..FF 00..FF byte word byte word byte +2 +2 +2 +2 +1 +2 +1 +2 +2 +3 PC-128/PC+1271) btjt [$10],#7,skip 00..FF Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx. 112/132 ST72141K ST7 ADDRESSING MODES (Cont'd) 9.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask Reset Interrupt Mask Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles 9.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 9.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 9.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 9.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value. Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function 113/132 ST72141K ST7 ADDRESSING MODES (Cont'd) 9.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 47. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes Long and Short Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Addition/subtraction operations Bit Compare Function SWAP CALL, JP Swap Nibbles Call or Jump subroutine 9.1.7 Relative Mode (Direct, Indirect) This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it. Available Relative Direct/ Indirect Instructions JRxx CALLR Function Conditional Jump Call Relative The relative addressing mode consists of two submodes: Relative (Direct) The offset follows the opcode. Relative (Indirect) The offset is defined in memory, of which the address follows the opcode. Short Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC Clear Function Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations 114/132 ST72141K 9.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Condition Code Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP be subdivided into 13 main groups as illustrated in the following table: Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. 115/132 ST72141K INSTRUCTION GROUPS (Cont'd) Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if ext. interrupt = 1 Jump if ext. interrupt = 0 Jump if H = 1 Jump if H = 0 Jump if I = 1 Jump if I = 0 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) H=1? H=0? I=1? I=0? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > jrf * Pop CC, A, X, PC inc X jp [TBL.w] reg, M H tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 0 I N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst M M M M Src H H H I N N N N N Z Z Z Z Z C C C 116/132 ST72141K INSTRUCTION GROUPS (Cont'd) Mnemo JRULE LD MUL NEG NOP OR POP Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack A=A+M pop reg pop CC PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Subtract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Subtraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I=0 C <= Dst <= C C => Dst => C S = Max allowed A=A-M-C C=1 I=1 C <= Dst <= 0 C <= Dst <= 0 0 => Dst => C Dst7 => Dst => C A=A-M reg, M reg, M reg, M reg, M A M 1 N N 0 N N N N 1 0 N Z Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 0 N N Z Z C C push Y C=0 A reg CC M M M M reg, CC 0 H I N Z C N Z Function/Example Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 N Z N Z 0 C Dst Src H I N Z C Dst[7..4] <=> Dst[3..0] reg, M tnz lbl1 S/W interrupt 117/132 ST72141K 10 ELECTRICAL CHARACTERISTICS 10.1 ABSOLUTE MAXIMUM RATINGS This product contains devices for protecting the inputs against damage due to high static voltages, however it is advisable to take normal precautions to avoid applying any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that VI and VO be higher than V SS and lower than V DD. Reliability is enhanced if unused inputs are connected to an appropriate logic voltage level (VDD or V SS). Symbol VDD - VSS VIN VOUT ESD IVDD_i IVSS_i Supply voltage Input voltage on true open drain pin Input voltage on any other pin Output voltage ESD susceptibility Total current into VDD_i (source) Total current out of VSS_i (sink) Ratings Power Considerations. The average chip-junction temperature, TJ, in Celsius can be obtained from: TJ = TA + PD x RthJA Where: TA = Ambient Temperature. RthJA =Package thermal resistance (junction-to ambient). PD = PINT + P PORT. PINT = IDD x VDD (chip internal power). PPORT =Port power dissipation determined by the user) Value 6.5 VSS - 0.3 to 6.5 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 2000 80 80 V V mA Unit V V Note: Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. General Warning: Direct connection to VDD or VSS of the RESET and I/O pins could damage the device in case of unintentional internal reset generation or program counter corruption (due to unwanted change of the I/O configuration). To guarantee safe conditions, this connection has to be done through a 10K typical pull-up or pull-down resistor. Thermal Characteristics Symbol RthJA TJmax TSTG PD Ratings Package thermal resistance Max. junction temperature Storage temperature range Power dissipation SO34 SDIP32 Value 75 60 150 -65 to +150 500 Unit C/W C C mW 118/132 ST72141K 10.2 RECOMMENDED OPERATING CONDITIONS GENERAL Symbol VDD fOSC Parameter Supply voltage Resonator oscillator frequency External clock source 1 Suffix Version TA Ambient temperature range 6 Suffix Version 3 Suffix Version 0 -40 -40 Conditions Min 4.0 8 or 16 2) 70 85 125 C Typ 1) Max 5.5 Unit V MHz 10.3 DC ELECTRICAL CHARACTERISTICS Recommended operating conditions with T A=-40 to +125oC, VDD-VSS=5V unless otherwise specified. Symbol Parameter Supply current in RUN mode 3) Supply current in SLOW mode 3) IDD Supply current in WAIT mode 4) Conditions fOSC = 8 MHz, fCPU = 4 MHz fOSC = 16 MHz, fCPU = 8 MHz fOSC = 8 MHz, fCPU = 250 kHz fOSC = 16 MHz, fCPU = 500 kHz fOSC = 8MHz, fCPU = 4 MHz fOSC = 16MHz, fCPU = 8 MHz Min Typ 1) 5 7 0.7 1 2 3.3 0.65 0.8 2 Max 8 12 1.1 1.7 3 5 1 1.4 200 Unit mA f = 8 MHz, fCPU = 250 kHz Supply current in SLOW WAIT mode 4) OSC fOSC = 16 MHz, fCPU = 500 kHz VRM Supply current in HALT mode 5) Data retention mode 6) ILOAD = 0mA (current on IOs) HALT mode A V 10.4 GENERAL TIMING CHARACTERISTICS Symbol tINST tIRT Parameter Instruction time Interrupt reaction time tIRT = tINST + 10 7) Conditions Min 2 10 Typ Max 12 22 Unit tCPU tCPU Notes: 1) Unless otherwise specified, typical data is based on TA=25C and VDD-VSS=5V. This data is provided only as design guidelines and is not tested. 2) Fixed frequencies required to obtain 4MHz for the motor control peripheral. 3) CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS, all peripherals switched off; clock input (OSC2) driven by external square wave. 4) All I/O pins in input mode with a static value at VDD or VSS, all peripherals switched off; clock input (OSC2) driven by external square wave. 5) All I/O pins in input mode with a static value at VDD or VSS. 6) Data based on characterization results, not tested in production. 7) tINST is the number of tCPU to finish the current instruction execution. 119/132 ST72141K 10.5 I/O PORT CHARACTERISTICS Recommended operating conditions with TA=-40 to +125oC and 4.5V 2) Conditions Min 0.7xVDD Typ 1) Max 0.3xVDD Unit V mV Input high level voltage 2) Schmitt trigger voltage hysteresis 3) Output low level voltage for standard I/O port pins I=-5mA I=-2mA I=-20mA I=-8mA I=-5mA I=-2mA VIN > VIH VIN < VIL VSS 400 1.3 0.5 1.3 0.5 VDD-2.0 VDD-0.8 20 50 40 120 80 240 1 200 5 -5 20 20 14.8 4) 14.4 4) 1 25 25 45.6 4) 45.9 4) VOL Output low level voltage for high sink I/O port pins Output high level voltage Pull-up equivalent resistor Input leakage current Static current consumption Single pin injected current Total injected current 7) (sum of all I/O and control pins) Output high to low level fall time Output low to high rise time External interrupt pulse time 8) V VOH RPU IL ISV IPINJ IINJ tOHL tOLH tITEXT k A Floating input mode Positive 5): VEXT >VDD Negative 6): VEXT ns tCPU Notes: 1) Unless otherwise specified, typical data is based on TA=25C and VDD-VSS=5V. This data is provided only as design guidelines and is not tested. 2) Data based on design simulations and/or technology characteristics, not tested in production. 3) Hysteresis voltage between Schmitt trigger switching levels. Based on characterisation results, not tested. 4) Data based on characterization results, not tested in production. 5) Positive injection (IINJ+) The IINJ+ is performed through protection diodes insulated from the substrate of the die. The true open-drain pins do not accept positive injection. In this case the maximum voltage rating must be respected. 6) ADC accuracy reduced by negative injection (IINJ- ) The IINJ- is performed through protection diodes NOT INSULATED from the substrate of the die. The drawback is a small leakage (a few A) induced inside the die when a negative injection is performed. This leakage is tolerated by the digital structure, but it acts on the analog line depending on the impedance versus a leakage current of a few A (if the MCU has an AD converter). The effect depends on the pin which is submitted to the injection. Of course, external digital signals applied to the component must have a maximum impedance close to 50K. Location of the negative current injection: - Pins with analog input capability are the most sensitive. IINJ- maximum is 0.8 mA (assuming that the impedance of the analog voltage is lower than 25K) - Pure digital pins can tolerate 1.6mA. In addition, the best choice is to inject the current as far as possible from the analog input pins. 7) When several inputs are submitted to a current injection, the maximum IINJ is the sum of the positive (or negative) currents (instantaneous values). These results are based on characterisation with IINJ maximum current injection on four I/ O port pins of the device. 8) To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source. 120/132 ST72141K 10.6 SUPPLY, RESET AND CLOCK CHARACTERISTICS 10.6.1 Supply Manager Recommended operating conditions with T A=-40 to +125oC and voltages referred to VSS. LOW VOLTAGE DETECTOR (LVD) Symbol VLVDr VLVDf VLVDhyst VtPOR IDD Parameter Reset release threshold Reset generation threshold VLVD Hysteresis 2) VDD rise time rate 3) LVD Supply Current Conditions VDD rise VDD fall VLVDr - VLVDf HALT mode Min 3.5 0.2 100 Typ 1) 4.05 3.75 250 Max 4.30 4.0 50 2004) Unit V mV V/ms A 10.6.2 RESET Sequence Manager Recommended operating conditions with T A=-40...+125oC and 4.5V tPULSE 20 10.6.3 Clock System Recommended operating conditions with T A=-40 to +125oC and voltages referred to VSS. EXTERNAL CLOCK SOURCE Symbol VOSC2h VOSC2l Parameter OSC2 input pin high level voltage OSC2 input pin low level voltage Conditions Square wave signal with ~50% Duty Cycle Min 0.7xVDD VSS Typ Max VDD 0.3xVDD Unit V CRYSTAL AND CERAMIC RESONATOR OSCILLATORS Symbol fOSC CLi IDD tSTART Parameter Oscillator Load Capacitor Supply Current Oscillator start-up time Frequency 6) Conditions RSmax=100 7) Min 8 15 8) Typ 5) Max Unit 16 MHz 18 21 6) pF 700 1100 4) A Depends on resonator quality. A typical value is 10ms Notes: 1) LVD typical data is based on TA=25C. This data is provided only as design guidelines and are not tested. 2) The VLVDhyst hysteresis is constant. 3) The VDD rise time rate condition is needed to ensure a correct device power-on reset. Not tested in production. 4) Data based on characterization results, not tested in production. 5) Unless otherwise specified, typical data is based on TA=25C and VDD-VSS=5V. This data is provided only as design guidelines and is not tested. 6) This data is based on typical a RSmax value. The oscillator selection can be optimized in terms of supply current with a high quality resonator. 7) RSmax is the equivalent serial resistor of the crystal or ceramic resonator. 8) Data based on design simulations and/or technology characteristics, not tested in production. 121/132 ST72141K 10.7 MEMORY AND PERIPHERAL CHARACTERISTICS EPROM Symbol WERASE tERASE UV lamp Erase Time Parameter Conditions Lamp wavelength 2537A UV lamp placed 1 inch from the device window without any interposed filters 15 Min Typ 15 20 Max Unit W-sec/cm2 min WATCHDOG Symbol tw(WDG) tWDGRST Parameter Watchdog time-out duration Watchdog RESET pulse width Conditions Min 12,288 fCPU=8MHz 1.54 500 Typ Max 786,432 98.3 Unit tCPU ms ns Recommended operating conditions with TA=-40 to +125oC and VDD-VSS=5V unless otherwise specified. MOTOR CONTROL Symbol VOFFSET VMTChyst tPROPAG Parameter Comparator offset error MCIA/B/C comparator hysteresis 2) Comparator propagation delay Reference voltage tolerance 30 VCREF resistance bridge tolerance 70 0.7 5 % 35 Conditions Min Typ 1) <10 80 Max 100 130 1 5 Unit mV mV s % k VREF VREF R1 R2 = R2 R1+R2 / Note: 1) Unless otherwise specified, typical data is based on TA = 25 C and VDD-VSS = 5 V. This data is provided only as design guidelines and are not tested. 2) The VMTChyst hysteresis is constant. Figure 64. Motor Control Comparator Characteristics V VREF+ MTChyst 2 VOFFSET VOFFSET VREF- VMTChyst 2 COMPARATOR VIN IDEAL REAL tPROPAG tPROPAG t 122/132 COMPARATOR OUTPUT ST72141K MEMORY AND PERIPHERAL CHARACTERISTICS (Cont'd) SPI Serial Peripheral Interface Value 1) Ref. Symbol fSPI 1 2 3 4 5 6 7 8 9 10 11 12 13 tSPI tLead tLag tSPI_H tSPI_L tSU tH tA tDis tV tHold tRise tFall Parameter SPI frequency SPI clock period Enable lead time Enable lag time Clock (SCK) high time Clock (SCK) low time Data set-up time Data hold time (inputs) Access time (time to data active from high impedance state) Disable time (hold time to high impedance state) Data valid Data hold time (outputs) Master Slave Master Slave Slave Slave Master Slave Master Slave Master Slave Master Slave Condition Min 1/128 dc 4 2 120 120 100 90 100 90 100 100 100 100 0 Slave 240 Master (before capture edge) Slave (after enable edge) Master (before capture edge) Slave (after enable edge) 0.25 120 0.25 0 100 100 100 100 ns tCPU ns tCPU ns ns s ns s 120 Max 1/4 1/2 Unit fCPU tCPU ns ns ns ns ns ns ns Rise time Outputs: SCK,MOSI,MISO (20% VDD to 70% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS Fall time Outputs: SCK,MOSI,MISO (70% VDD to 20% VDD, CL = 200pF) Inputs: SCK,MOSI,MISO,SS Figure 65. SPI Master Timing Diagram CPHA=0, CPOL=0 2) SS (INPUT) SCK (OUTPUT) 4 MISO (INPUT) MOSI (OUTPUT) 6 D7-IN 7 D7-OUT 11 1 13 12 5 D6-IN D6-OUT D0-IN D0-OUT VR000109 10 Notes: 1) Data based on characterization results, not tested in production. 2) Measurement points are VOL, VOH, VIL and VIH in the SPI timing diagram 123/132 ST72141K MEMORY AND PERIPHERAL CHARACTERISTICS (Cont'd) Figure 66. SPI Master Timing Diagram CPHA=0, CPOL=1 1) SS (INPUT) SCK (OUTPUT) MISO (INPUT) MOSI (OUTPUT) 1 13 5 6 10 D7-IN 7 D7-OUT 11 4 D6-IN D6-OUT D0-IN D0-OUT VR000110 12 Figure 67. SPI Master Timing Diagram CPHA=1, CPOL=0 1) SS (INPUT) SCK (OUTPUT) MISO (INPUT) MOSI (OUTPUT) 1 13 4 6 10 7 D7-IN 11 D6-IN D0-IN VR000107 5 D7-OUT D6-OUT D0-OUT 12 Figure 68. SPI Master Timing Diagram CPHA=1, CPOL=1 SS (INPUT) SCK (OUTPUT) MISO (INPUT) MOSI (OUTPUT) 1 12 5 6 10 4 D7-IN 7 D7-OUT 11 D6-IN D6-OUT 1) 13 D0-IN D0-OUT VR000108 Note: 1) Measurement points are VOL, VOH, VIL and VIH in the SPI timing diagram 124/132 ST72141K MEMORY AND PERIPHERAL CHARACTERISTICS (Cont'd) Measurement points are V OL, VOH, VIL and VIH in the SPI Timing Diagram Figure 69. SPI Slave Timing Diagram CPHA=0, CPOL=0 1) SS (INPUT) SCK (INPUT) MISO HIGH-Z (OUTPUT) 8 MOSI (INPUT) 6 2 1 13 4 D7-OUT 10 D7-IN 7 VR000113 D6-IN 5 D6-OUT 11 D0-IN D0-OUT 9 12 3 Figure 70. SPI Slave Timing Diagram CPHA=0, CPOL=1 1) SS (INPUT) SCK (INPUT) HIGH-Z MISO (OUTPUT) 8 MOSI (INPUT) 6 2 1 12 5 D7-OUT 10 D7-IN 7 VR000114 D6-IN 4 D6-OUT 11 D0-IN D0-OUT 9 13 3 Figure 71. SPI Slave Timing Diagram CPHA=1, CPOL=0 1) SS (INPUT) 2 SCK (INPUT) HIGH-Z MISO (OUTPUT) MOSI (INPUT) 8 D7-IN 6 7 VR000111 4 5 D7-OUT 10 D6-IN D6-OUT 11 D0-IN D0-OUT 9 1 13 12 3 Figure 72. SPI Slave Timing Diagram CPHA=1, CPOL=1 1) SS (INPUT) 2 SCK (INPUT) HIGH-Z MISO (OUTPUT) MOSI (INPUT) 8 D7-IN 6 7 VR000112 5 4 D7-OUT 10 D6-IN D6-OUT 11 D0-IN D0-OUT 9 1 12 13 3 Note: 1) Measurement points are VOL, VOH, VIL and VIH in the SPI timing diagram 125/132 ST72141K MEMORY AND PERIPHERAL CHARACTERISTICS (Cont'd) ADC Analog to Digital Converter (8-bit) Symbol |TUE| OE GE |DLE| |ILE| VAIN IADC tSTAB tLOAD tCONV RAIN RADC Parameter Total unadjusted error Offset error 3) 3) Conditions Min Typ 1) Max 2 Unit Gain Error 3) Differential linearity error Integral linearity error 3) Conversion range voltage A/D conversion supply current Stabilization time after ADC enable Sample capacitor loading time Hold conversion time External input resistor Internal input resistor 3) TA=25C,VDD=VDDA=5V,2) fCPU=8MHz -1 -2 1 2 1 2 LSB VSSA 1 VDDA 30 V mA s s 1/fADC s 1/fADC fADC=fCPU=4MHz VDD=VDDA=5V 8 32 8 32 20 4) 18 22 k k pF CSAMPLE Sample capacitor Notes: 1) Unless otherwise specified, typical data is based on TA=25C and VDD-VSS=5V. This data is provided only for design guidelines and is not tested. 2) Tested in production at TA=25C, characterized over all temperature range. 3) ADC Accuracy vs. Negative Injection Current: For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6A and the effect on the ADC accuracy is a loss of 1 LSB by 10K increase of the external analog source impedance. These measurement results and recommendations have been done under worst conditions for injection: - negative injection - injection to an Input with analog capability, adjacent to the enabled Analog Input - at 5V VDD supply, and worst case temperature. 4) Data based on characterization results, not tested in production. 126/132 ST72141K MEMORY AND PERIPHERAL CHARACTERISTICS (Cont'd) VDD RAIN VAIN Px.x/AINx Cpin 5pF VT = 0.6V leakage 1A SS VT = 0.6V Sampling Switch RSS 2 Chold 6 pF Cpin VT SS Chold = input capacitance = threshold voltage = sampling switch = sample/hold capacitance leakage = leakage current at the pin due to various junctions VSS Digital Result ADCDR 255 254 253 1LSB i deal V -V DDA SSA = ---------------------------------------256 (2) 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSB (ideal) OE ILE DLE TUE (3) (1) GE (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line TUE=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. OE=Offset Error: deviation between the first actual transition and the first ideal one. GE=Gain Error: deviation between the last ideal transition and the last actual one. DLE=Differential Linearity Error: maximum deviation between actual steps and the ideal one. ILE=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Vin (LSBideal) 5 6 7 253 254 255 256 VDDA 127/132 ST72141K 11 GENERAL INFORMATION 11.1 PACKAGE MECHANICAL DATA Figure 73. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width mm Min 3.56 0.51 3.05 0.36 0.76 0.20 27.43 7.62 Typ Max Min 0.020 3.56 4.57 0.120 0.140 0.180 0.46 0.58 0.014 0.018 0.023 1.02 1.40 0.030 0.040 0.055 0.25 0.36 0.008 0.010 0.014 28.45 1.080 1.100 1.120 8.89 9.40 0.300 0.350 0.370 1.78 10.16 12.70 1.40 2.54 Number of Pins N 32 0.070 0.400 0.500 0.055 inches Typ Max Dim. E eC A A1 A2 A 3.76 5.08 0.140 0.148 0.200 A2 b E1 C eA eB A1 L b1 C D E E1 e eA eB eC L b2 D b e 9.91 10.41 11.05 0.390 0.410 0.435 3.05 3.81 0.100 0.120 0.150 Figure 74. 34-Pin Plastic Small Outline Package, Shrink 300-mil Width Dim. hx 4 5x L A 1 A a B D e C mm Min 2.464 0.127 0.356 0.231 17.72 9 7.417 1.016 10.16 0 0.635 0 0.610 10.41 0.400 4 0.737 0.025 8 0 1.016 0.024 Typ Max Min 2.642 0.097 0.292 0.005 0.483 0.014 0.318 0.009 18.05 0.698 9 7.595 0.292 inches Typ Max 0.104 0.012 0.019 0.013 0.711 0.299 0.040 0.410 0.029 8 0.040 A A1 B C D E e E H H h L N Number of Pins 34 128/132 ST72141K 11.2 ORDERING INFORMATION Transfer Of Customer Code Customer code is made up of the ROM contents and the list of the selected options (if any). The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. All unused bytes must be set to FFh. Figure 75. ROM Factory Coded Device Types TEMP. DEVICE PACKAGE RANGE / XXX Code name (defined by STMicroelectronics) 6= industrial -40 to +85 C 3= automotive -40 to +125 C The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points. B= Plastic DIP M= Plastic SOIC ST72141K2 Figure 76. OTP User Programmable Device Types TEMP. DEVICE PACKAGE RANGE XXX Code name (defined by STMicroelectronics) 6= industrial -40 to +85 C 3= automotive -40 to +125 C B= Plastic DIP M= Plastic SOIC ST72T141K2 129/132 ST72141K MICROCONTROLLER OPTION LIST ............................. ............................. ............................. Contact ............................. Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STMicroelectronics references Device: [ ] ST72141K2 Package: [ ] SO34 Conditioning: Customer Address [ ] SDIP32 [ ] Tube [ ] Tape & Reel (not available for SDIP packages) [ ] -40 to 85C [ ] Enabled [ ] -40 to 125C [ ] Disabled Temperature Range: Readout Protection: Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _" Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character count: DIP32 10 SO34 13 Comments Notes Signature Date : ............................. ............................. ............................. 130/132 ST72141K 12 SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Rev. 1.8 Main Changes Added VtPOR in section 10.6.1 on page 121 Modified VMTChyst and Voffset in section 10.7 on page 122 Modified Option list in Section 11.2 Oct 01 Date 131/132 ST72141K Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2002 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 132/132 |
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